Abstract: Apparatus might include an array of memory cells comprising a plurality of strings of series-connected memory cells and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to perform a sense operation on a selected memory cell of a string of series-connected memory cells, and to discharge access lines connected to the string of series-connected memory cells in a defined manner following the sense operation.

Abstract: Apparatus might include an array of memory cells comprising a plurality of strings of series-connected memory cells and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to perform a sense operation on a selected memory cell of a string of series-connected memory cells, and to discharge access lines connected to the string of series-connected memory cells in a defined manner following the sense operation.

Abstract: Memories might include an array of memory cells comprising a plurality of strings of series-connected memory cells and a controller for access of the array of memory cells, wherein the controller is configured to perform a sense operation on a particular memory cell of a string of series-connected memory cells, discharge the access line for a second memory cell of the string of series-connected memory cells to a first voltage level and discharge the access line for the particular memory cell to a second voltage level higher than the first voltage level after completion of the sense operation, and discharge the access line for a third memory cell of the string of series-connected memory cells to a third voltage level lower than the second voltage level and higher than the first voltage level after initiating the discharge of the access line for the particular memory cell.

Abstract: Memories might include an array of memory cells comprising a plurality of strings of series-connected memory cells and a controller for access of the array of memory cells, wherein the controller is configured to perform a sense operation on a particular memory cell of a string of series-connected memory cells, discharge the access line for a second memory cell of the string of series-connected memory cells to a first voltage level and discharge the access line for the particular memory cell to a second voltage level higher than the first voltage level after completion of the sense operation, and discharge the access line for a third memory cell of the string of series-connected memory cells to a third voltage level lower than the second voltage level and higher than the first voltage level after initiating the discharge of the access line for the particular memory cell.

Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include performing a sense operation on a particular memory cell of a string of series-connected memory cells, discharging the respective access line for a second memory cell of the string of series-connected memory cells to a first voltage level, discharging the respective access line for the particular memory cell to a second voltage level higher than the first voltage level, and discharging the respective access line for a third memory cell of the string of series-connected memory cells to a third voltage level lower than the second voltage level and higher than the first voltage level.

Abstract: A method for erasing an electrically programmable and erasable non-volatile memory cell having a control electrode, an electrically-insulated electrode and a first electrode. The method provides for coupling the control electrode to a first voltage supply and coupling the first electrode to a second voltage supply. The first voltage supply and the second voltage supply are suitable to cause tunneling of electric charges between the electrically-insulated electrode and the first electrode. The method also provides for a constant current to flow between the second voltage supply and the first electrode of the memory cell for at least part of an erasing time of the memory cell, the constant current having a prescribed value.

Abstract: A process for simultaneously fabricating a flash-EEPROM memory and circuit transistors using a DPCC process. A first polysilicon layer is not removed from the circuit area, and the gate regions of a circuit transistors are formed by shorting first and second polysilicon layers. A thin tunnel oxide layer of the memory cells is formed using the same mask provided for implanting boron into the cell area of the substrate. Following implantation and without removing the mask, the gate oxide formed previously over the whole surface of the wafer is removed from the cell area; the boron implant mask is removed; and tunnel oxidation is performed to increase the thickness of the tunnel oxide by a desired amount, and to slightly increase the thickness of the oxide in the transistor area.

Abstract: After growth of gate oxide, deposit and separation of a first polycrystalline silicon layer, growth of dielectric oxide and removal thereof from the transistor area, and deposit of a second polycrystalline layer, a single mask makes possible first etching of the second silicon layer and of the dielectric oxide and then of the first silicon layer of the gate oxide at the sides of the cell and transistor areas.