Abstract: A line interface for combining a broad-band XDSL signal and a voice-band telephone signal in a copper duplex cable, where the voice-band signal, over and above the voice signal, carries a DC feed for the user telephone and, during the call phase, also a ring signal. The XDSL signal and the voice signal are coupled to at least one primary winding of a line transformer of which the secondary winding pilots the telephone duplex cable. The secondary winding is not DC-coupled with the duplex cable and the ring and feed signals are injected into the duplex cable by a circuit realized in high-voltage technology and arranged in parallel with the secondary winding. A further inductive winding performs the function of compensating the flow variations induced in the core of the line transformer during the call phase.

Abstract: A first N-channel transistor (M1) and a second N-channel transistor (M2) are cascode connected and the source electrode of the first transistor is connected to the ground; a third P-channel transistor (M3) and a fourth P-channel transistor (M4) are also cascode connected, and the source of the fourth transistor is connected to a supply voltage; the drains of the second and third transistors (M2, M3) are mutually connected to act as output terminal. According to the invention, the absolute values of the threshold voltages of the second and third transistors are lower than the threshold voltages of the first and fourth transistors, and the gates of the first and second transistors are furthermore mutually connected to act as input terminal for a voltage signal, while the gates of said third and fourth transistors are mutually connected to act as input terminal for a bias voltage.

Abstract: In a chain of fully differential amplifiers, having at least two cascaded amplifiers, the stabilization of the output common mode voltage of an amplifier is implemented by sensing the value of such a voltage by means of a dedicated terminal connected to a circuit node corresponding to the connected in common sources of the input differential pair of transistors of an amplifier which follows in the chain of cascaded amplifiers. Such a voltage is compared with a reference voltage to which, by means of a level shifting circuit, a voltage equivalent to the threshold voltage of the transistors forming the input pair is subtracted thus obtaining an error signal of the output common voltage of the amplifier to be stabilized which may be applied to a dedicated control terminal thereof. The system of the invention provides for the sensing of the output common mode voltage without loading the outputs of the amplifier to be stabilized and it is more easily implemented than known systems.

Abstract: A low offset voltage follower circuit includes substantially identical first and second N-channel MOS transistors having their source electrodes connected to a negative terminal of a supply voltage source via a third N-channel MOS transistor whose gate electrode is connected to a first reference voltage, and having their drain electrodes respectively connected to a positive terminal of the supply voltage source via fourth and fifth P-channel MOS transistors whose gate electrodes are connected to a second reference voltage. The gate electrode of the first transistor forms an input terminal of the follower circuit and the gate and drain electrodes of the second transistor are connected together to form an output terminal of the follower circuit.

Abstract: An interface circuit with MOS-type transistors for timing signal generators with two non-overlapping phases made up of two identical twin circuits, each having a final stage of the type including two transistors connected in series between the two terminals of a supply voltage generator and a bootstrap capacitor. Each of the two twin circuits includes a logic NOR circuit and a logic AND circuit which control, respectively, the charging and discharging of the capacitor through a suitable switching circuit connected to both terminals thereof. In each circuit, a memory circuit element is connected to the logic circuits. The memory circuit element is sensitive to the output signals of both twin circuits and enables the charging and discharging of the bootstrap capacitor at successive, logically produced time intervals which occur between the pulses of the output signals of both twin circuits.

Abstract: An output interface which includes a capacitor which is charged to a relatively high voltage by a voltage source which may have a high internal impedance, and a switching circuit which is controlled by an output of the associated logic circuit and which connects the capacitor with a gate electrode of a transistor of the final stage of the interface in order to bias it at a higher voltage than that of the power supply only during a prespecified logic state of the logic circuit and which keeps the capacitor essentially isolated (i.e.--floating) during any other logic state.