Patents by Inventor Daniele Fronte

Daniele Fronte has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10998306
    Abstract: A circuit for protecting an integrated circuit against fault injection attacks includes an element including a dielectric which is destroyed, resulting in the occurrence of a short-circuit. The element is connected between two terminals that receive a power supply voltage of the integrated circuit.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: May 4, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Daniele Fronte, Pierre-Yvan Liardet, Alexandre Sarafianos
  • Publication number: 20200020650
    Abstract: An electronic chip includes a first well having a first PN junction located therein, a second buried well located under and separated from the first well, and a first region forming a second PN junction with the second well. A detection circuit is coupled to the first well and configured to output a digital signal that has a first logic value when a potential difference within the first region is above a threshold and a second logic value when the potential difference within the first region is below the threshold.
    Type: Application
    Filed: July 5, 2019
    Publication date: January 16, 2020
    Inventors: Alexandre Sarafianos, Bruno Nicolas, Daniele Fronte
  • Publication number: 20190355673
    Abstract: The disclosure concerns an electronic chip including a resistive region and a first switch of selection of a first area in contact with the resistive region.
    Type: Application
    Filed: May 10, 2019
    Publication date: November 21, 2019
    Inventors: Alexandre SARAFIANOS, Bruno NICOLAS, Daniele FRONTE
  • Publication number: 20190268134
    Abstract: A cryptographic circuit performs a substitution operation of a cryptographic algorithm based on a scrambled substitution table. For each set of one or more substitution operations of the cryptographic algorithm, the circuit performs a series of sets of one or more substitution operations of which: one is a real set of one or more substitution operations defined by the cryptographic algorithm, the real set of one or more substitution operations being based on input data modified by a real scrambling key; and one or more others are dummy sets of one or more substitution operations, each dummy set of one or more dummy substitution operations being based on input data modified by a different false scrambling key.
    Type: Application
    Filed: February 21, 2019
    Publication date: August 29, 2019
    Inventors: Daniele FRONTE, Yanis LINGE, Thomas ORDAS
  • Publication number: 20190244915
    Abstract: A semiconductor substrate of an integrated circuit is protected by a coating. The semiconductor includes a front face and a rear face. To detect a breach of the integrity of a semiconductor substrate of an integrated circuit from the rear face, an opening of the coating facing the rear face of the substrate is detected. In response thereto, an alarm is generated. The detection is performed by making resistance measurements with respect to the semiconductor substrate and comparing the measured resistance to a nominal resistive value of the semiconductor substrate.
    Type: Application
    Filed: February 5, 2019
    Publication date: August 8, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre SARAFIANOS, Bruno NICOLAS, Daniele FRONTE
  • Publication number: 20190051643
    Abstract: A circuit for protecting an integrated circuit against fault injection attacks includes an element including a dielectric which is destroyed, resulting in the occurrence of a short-circuit. The element is connected between two terminals that receive a power supply voltage of the integrated circuit.
    Type: Application
    Filed: August 10, 2018
    Publication date: February 14, 2019
    Inventors: Daniele Fronte, Pierre-Yvan Liardet, Alexandre Sarafianos
  • Patent number: 8301905
    Abstract: A system and method for encrypting data. The system includes a controller and a processing element (PE) array coupled to the controller. The PE array is operative to perform one or more of encryption functions and decryption functions using an encryption algorithm. According to the system and method disclosed herein, by utilizing the PE array, the system encrypts and decrypts data efficiently and flexibly.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: October 30, 2012
    Assignee: Inside Secure
    Inventors: Daniele Fronte, Eric Payrat, Annie Perez
  • Publication number: 20080062803
    Abstract: A system and method for encrypting data. The system includes a controller and a processing element (PE) array coupled to the controller. The PE array is operative to perform one or more of encryption functions and decryption functions using an encryption algorithm. According to the system and method disclosed herein, by utilizing the PE array, the system encrypts and decrypts data efficiently and flexibly.
    Type: Application
    Filed: September 8, 2006
    Publication date: March 13, 2008
    Inventors: Daniele Fronte, Eric Payrat, Annie Perez
  • Patent number: 7337300
    Abstract: A method is provided for processing a virtual address for a program requesting a DMA transfer. The program is designed to be run in user mode on a system on a chip that includes a central processing unit, a memory management unit, and a DMA controller. The virtual address is a source virtual address or a destination virtual address and has a size of N bits. According to the method, the virtual address is divided into at least two fields of bits. For each of the fields, there is created an N-bit address word comprising a prefix having a given value associated with the field and having more than 1 bit, and the field. The DMA controller is programmed using multiple store instructions that include one store instruction relating to each of the address words created.
    Type: Grant
    Filed: June 16, 2005
    Date of Patent: February 26, 2008
    Assignee: STMicroelectronics SA
    Inventors: Daniele Fronte, Jean Nicolai, Albert Martinez
  • Publication number: 20060010262
    Abstract: A method is provided for processing a virtual address for a program requesting a DMA transfer. The program is designed to be run in user mode on a system on a chip that includes a central processing unit, a memory management unit, and a DMA controller. The virtual address is a source virtual address or a destination virtual address and has a size of N bits. According to the method, the virtual address is divided into at least two fields of bits. For each of the fields, there is created an N-bit address word comprising a prefix having a given value associated with the field and having more than 1 bit, and the field. The DMA controller is programmed using multiple store instructions that include one store instruction relating to each of the address words created.
    Type: Application
    Filed: June 16, 2005
    Publication date: January 12, 2006
    Applicant: STMICROELECTRONICS SA
    Inventors: Daniele Fronte, Jean Nicolai, Albert Martinez