Patents by Inventor Daniele Gilkes

Daniele Gilkes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Copper silicide passivation for improved reliability
    Patent number: 6869873
    Abstract: A silane passivation process, carried out in-situ together with the formation of a subsequent dielectric film, converts the exposed Cu surfaces of a Cu interconnect structure, to copper silicide. The copper silicide suppresses Cu diffusion and electromigration and serves as a barrier material in regions where contact to further conductive material is made. An entire copper surface of a copper interconnect structure may be silicided or a local portion of the surface silicided after an opening is formed in an overlying dielectric to expose a portion of the copper surface.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: March 22, 2005
    Assignee: Agere Systems Inc.
    Inventors: Robert Wayne Bradshaw, Daniele Gilkes, Sailesh Mansinh Merchant, Deepak A. Ramappa, Kurt George Steiner
  • Copper silicide passivation for improved reliability
    Publication number: 20040097075
    Abstract: A silane passivation process, carried out in-situ together with the formation of a subsequent dielectric film, converts the exposed Cu surfaces of a Cu interconnect structure, to copper silicide. The copper silicide suppresses Cu diffusion and electromigration and serves as a barrier material in regions where contact to further conductive material is made. An entire copper surface of a copper interconnect structure may be silicided or a local portion of the surface silicided after an opening is formed in an overlying dielectric to expose a portion of the copper surface.
    Type: Application
    Filed: June 30, 2003
    Publication date: May 20, 2004
    Inventors: Robert Wayne Bradshaw, Daniele Gilkes, Sailesh Mansinh Merchant, Deepak A. Ramappa, Kurt George Steiner
  • Microelectronic device layer deposited with multiple electrolytes
    Patent number: 6703712
    Abstract: A microelectronic device (24) is formed by plating a layer of material (36) to fill a cavity (28) formed in a substrate (26). The layer of material has a plurality of regions (42, 44, 46) with respective chemical compositions formed by varying the chemical composition of the plating solution as the layer of material is being deposited. In this manner, expensive additives necessary to achieve desired properties within the cavity may be omitted from the region (46) of overfill that will be removed by a later planarization process.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: March 9, 2004
    Assignee: Agere Systems, Inc.
    Inventors: Daniele Gilkes, Minseok Oh, Sailesh M. Merchant
  • Microelectronic device layer deposited with multiple electrolytes
    Publication number: 20030089986
    Abstract: A microelectronic device (24) is formed by plating a layer of material (36) to fill a cavity (28) formed in a substrate (26). The layer of material has a plurality of regions (42, 44, 46) with respective chemical compositions formed by varying the chemical composition of the plating solution as the layer of material is being deposited. In this manner, expensive additives necessary to achieve desired properties within the cavity may be omitted from the region (46) of overfill that will be removed by a later planarization process.
    Type: Application
    Filed: November 13, 2001
    Publication date: May 15, 2003
    Inventors: Daniele Gilkes, Minseok Oh, Sailesh M. Merchant