Abstract: A hardware-programmable digital signal path component for processing events from sensor mixed signal devices. A system includes a mixed signal component and a reconfigurable signal path component. The mixed signal component includes a group of sensor devices and generates one or more events from among the group of sensor devices. The signal path component receives the event(s), and includes a control unit component and a digital signal processor (DSP) component. The control unit component includes a programmable function enable mechanism, and distributes the received event(s) in combination with one or more functions among a set of predefined functions enabled by the programmable function enable mechanism. The DSP component is configured to perform one or more operations associated with the distributed event(s) in accordance with the enabled function(s).

Abstract: A hardware-programmable digital signal path component for processing events from sensor mixed signal devices. A system includes a mixed signal component and a reconfigurable signal path component. The mixed signal component includes a group of sensor devices and generates one or more events from among the group of sensor devices. The signal path component receives the event(s), and includes a control unit component and a digital signal processor (DSP) component. The control unit component includes a programmable function enable mechanism, and distributes the received event(s) in combination with one or more functions among a set of predefined functions enabled by the programmable function enable mechanism. The DSP component is configured to perform one or more operations associated with the distributed event(s) in accordance with the enabled function(s).

Abstract: An integrated circuit coupled to an external serial bus is presented. A method for prefetching data from an external serial bus is presented. The integrated circuit comprises a serial interface, a data cache, and a prefetch control unit. The serial interface detects a data address on the serial bus and reads data elements from data storage units. The data storage units may be internal or external to the integrated circuit. The data cache is coupled to the serial interface via an internal bus. The prefetch control unit instructs the serial interface to prefetch a data element associated with the data address by reading the data element from a target data storage unit associated with the data address. The data element and the data address are written to the data cache. When a read request is detected, the data element can be quickly accessed from the data cache.

Abstract: A distributed power management system comprising at least two power management integrated circuits PMICs is presented. A master power management integrated circuit PMIC supplies power to a subsystem of an electronic device based on a current state of a master finite state machine FSM executed by the master PMIC. A slave power management integrated circuit PMIC executes a slave finite state machine FSM and supplies power to another subsystem based on the current state of the master FSM. For synchronizing the operation of both PMIC, the master PMIC transmits, to the slave PMIC, synchronization information indicative of at least one of an input signal of the master FSM, a state of the master FSM, a state transition of the master FSM, and an output signal generated by the master FSM. A distributed power management method is presented which is carried out by a master PMIC and a slave PMIC.

Abstract: A distributed power management system comprising at least two power management integrated circuits PMICs is presented. A master power management integrated circuit PMIC supplies power to a subsystem of an electronic device based on a current state of a master finite state machine FSM executed by the master PMIC. A slave power management integrated circuit PMIC executes a slave finite state machine FSM and supplies power to another subsystem based on the current state of the master FSM. For synchronizing the operation of both PMIC, the master PMIC transmits, to the slave PMIC, synchronization information indicative of at least one of an input signal of the master FSM, a state of the master FSM, a state transition of the master FSM, and an output signal generated by the master FSM. A distributed power management method is presented which is carried out by a master PMIC and a slave PMIC.

Abstract: An integrated circuit coupled to an external serial bus is presented. A method for prefetching data from an external serial bus is presented. The integrated circuit comprises a serial interface, a data cache, and a prefetch control unit. The serial interface detects a data address on the serial bus and reads data elements from data storage units. The data storage units may be internal or external to the integrated circuit. The data cache is coupled to the serial interface via an internal bus. The prefetch control unit instructs the serial interface to prefetch a data element associated with the data address by reading the data element from a target data storage unit associated with the data address. The data element and the data address are written to the data cache. When a read request is detected, the data element can be quickly accessed from the data cache.

Abstract: In a multi-phase power supply voltage regulator functioning at a nominal switching frequency, one or more phases are kept off for optimizing energy efficiency at relatively low load conditions. Reactivation of stand-by phases in response to a load increase transient is made more efficiently by exploiting information already present in the output voltage control loop. The technique comprises a) deriving from the control loop information on the equivalent nominal switching frequency given by the product of the nominal switching frequency by the number of active phases; b) updating at every beat of a clock signal the instantaneous value of the equivalent switching frequency; c) determining the band of equivalent switching frequency values to which the instantaneous value belongs; d) logically combining the equivalent switching frequency information with a determined band of output current level, for switching on one or more stand-by phases in response to a load increase transient.

Abstract: A switching voltage regulator including a comparison module configured to receive a reference voltage and a feedback voltage and to generate a comparison signal corresponding to a difference between the reference voltage and the feedback voltage, an offset module configured to generate an offset signal based on a number of active phases of the voltage regulator, an adder configured to generate a control signal based on the comparison signal and the offset signal, a plurality of pulse-width-modulated (PWM) power stages, and a control module configured to control the plurality of PWM power stages based at least in part on the control signal generated by the adder.

Abstract: A switching voltage regulator includes a comparison module configured to receive a reference voltage and a feedback voltage and to generate a comparison signal based on a difference between the reference voltage and the feedback voltage, and a control module configured to generate a gain control threshold signal based on at least one of the reference voltage and the feedback voltage. The control module may be configured to control a duration of a PWM pulse based on the at least one of the reference voltage and the feedback voltage. The feedback voltage may a regulated output voltage of the switching voltage regulator. The switching voltage regulator may be implemented in an analog or a digital manner.

Abstract: In a multi-phase power supply voltage regulator functioning at a nominal switching frequency, one or more phases are kept off for optimizing energy efficiency at relatively low load conditions. Reactivation of stand-by phases in response to a load increase transient is made more efficiently by exploiting information already present in the output voltage control loop. The technique comprises a) deriving from the control loop information on the equivalent nominal switching frequency given by the product of the nominal switching frequency by the number of active phases; b) updating at every beat of a clock signal the instantaneous value of the equivalent switching frequency; c) determining the band of equivalent switching frequency values to which the instantaneous value belongs; d) logically combining the equivalent switching frequency information with a determined band of output current level, for switching on one or more stand-by phases in response to a load increase transient.

Abstract: A circuit may generate a clock signal with a variable period given by a ratio between an initial switching period and a number of phase circuits through which a current of a multi-phase PWM voltage converter flows. The circuit may include an adjustable current generator driven by a signal representing the number of phase circuits through which the current flows and configured to generate a current proportional to the number of phase circuits through which the current flows, and a tank capacitor charged by the adjustable current generator. The circuit may include a comparator of a voltage on the tank capacitor with a threshold value configured to generate a pulse of the clock signal when the threshold value is attained, and a discharge path of the tank capacitor, the discharge path being enabled during the pulses of the clock signal.

Abstract: A switching voltage regulator includes a comparison module configured to receive a reference voltage and a feedback voltage and to generate a comparison signal based on a difference between the reference voltage and the feedback voltage, and a control module configured to generate a gain control threshold signal based on at least one of the reference voltage and the feedback voltage. The control module may be configured to control a duration of a PWM pulse based on the at least one of the reference voltage and the feedback voltage. The feedback voltage may a regulated output voltage of the switching voltage regulator. The switching voltage regulator may be implemented in an analog or a digital manner.

Abstract: A switching voltage regulator including a comparison module configured to receive a reference voltage and a feedback voltage and to generate a comparison signal corresponding to a difference between the reference voltage and the feedback voltage, an offset module configured to generate an offset signal based on a number of active phases of the voltage regulator, an adder configured to generate a control signal based on the comparison signal and the offset signal, a plurality of pulse-width-modulated (PWM) power stages, and a control module configured to control the plurality of PWM power stages based at least in part on the control signal generated by the adder.

Abstract: A circuit may generate a clock signal with a variable period given by a ratio between an initial switching period and a number of phase circuits through which a current of a multi-phase PWM voltage converter flows. The circuit may include an adjustable current generator driven by a signal representing the number of phase circuits through which the current flows and configured to generate a current proportional to the number of phase circuits through which the current flows, and a tank capacitor charged by the adjustable current generator. The circuit may include a comparator of a voltage on the tank capacitor with a threshold value configured to generate a pulse of the clock signal when the threshold value is attained, and a discharge path of the tank capacitor, the discharge path being enabled during the pulses of the clock signal.

Abstract: A circuit may generate a clock signal with a variable period given by a ratio between an initial switching period and a number of phase circuits through which a current of a multi-phase PWM voltage converter flows. The circuit may include an adjustable current generator driven by a signal representing the number of phase circuits through which the current flows and configured to generate a current proportional to the number of phase circuits through which the current flows, and a tank capacitor charged by the adjustable current generator. The circuit may include a comparator of a voltage on the tank capacitor with a threshold value configured to generate a pulse of the clock signal when the threshold value is attained, and a discharge path of the tank capacitor, the discharge path being enabled during the pulses of the clock signal.

Abstract: A circuit may generate a clock signal with a variable period given by a ratio between an initial switching period and a number of phase circuits through which a current of a multi-phase PWM voltage converter flows. The circuit may include an adjustable current generator driven by a signal representing the number of phase circuits through which the current flows and configured to generate a current proportional to the number of phase circuits through which the current flows, and a tank capacitor charged by the adjustable current generator. The circuit may include a comparator of a voltage on the tank capacitor with a threshold value configured to generate a pulse of the clock signal when the threshold value is attained, and a discharge path of the tank capacitor, the discharge path being enabled during the pulses of the clock signal.