Patents by Inventor Daniele Leonelli

Daniele Leonelli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Tunnel transistor, logical gate including the transistor, static random-access memory using the logical gate and method for making such a tunnel transistor
    Patent number: 8576614
    Abstract: A tunnel transistor is provided including a drain, a source and at least a first gate for controlling current between the drain and the source, wherein the first sides of respectively the first and the second gate dielectric material are positioned substantially along and substantially contact respectively the first and the second semiconductor part.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: November 5, 2013
    Assignees: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&D
    Inventors: Marc Heyns, Cedric Huyghebaert, Anne S. Verhulst, Daniele Leonelli, Rita Rooyackers, Wim Dehaene
  • Method of manufacturing a complementary nanowire tunnel field effect transistor semiconductor device
    Patent number: 8415209
    Abstract: The present disclosure provides a method for manufacturing at least one nanowire Tunnel Field Effect Transistor (TFET) semiconductor device. The method comprises providing a stack comprising a layer of channel material with on top thereof a layer of sacrificial material, removing material from the stack so as to form at least one nanowire from the layer of channel material and the layer of sacrificial material, and replacing the sacrificial material in the at least one nanowire by heterojunction material. A method according to embodiments of the present disclosure is advantageous as it enables easy manufacturing of complementary TFETs.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: April 9, 2013
    Assignees: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&D
    Inventors: Rita Rooyackers, Daniele Leonelli, Anne Vandooren, Anne S. Verhulst, Roger Loo, Stefan De Gendt
  • TUNNEL TRANSISTOR, LOGICAL GATE COMPRISING THE TRANSISTOR, STATIC RANDOM-ACCESS MEMORY USING THE LOGICAL GATE AND METHOD FOR MAKING SUCH A TUNNEL TRANSISTOR
    Publication number: 20130064005
    Abstract: A tunnel transistor is provided comprising a drain, a source and at least a first gate for controlling current between the drain and the source, wherein the first sides of respectively the first and the second gate dielectric material are positioned substantially along and substantially contact respectively the first and the second semiconductor part.
    Type: Application
    Filed: August 16, 2012
    Publication date: March 14, 2013
    Applicants: Katholieke Universiteit Leuven, K.U. LEUVEN R&D, IMEC
    Inventors: Marc Heyns, Cedric Huyghebaert, Anne S. Verhulst, Daniele Leonelli, Rita Rooyackers, Wim Dehaene
  • METHOD OF MANUFACTURING A VERTICAL TFET
    Publication number: 20110253981
    Abstract: The present disclosure provides a method for manufacturing at least one nanowire Tunnel Field Effect Transistor (TFET) semiconductor device. The method comprises providing a stack comprising a layer of channel material with on top thereof a layer of sacrificial material, removing material from the stack so as to form at least one nanowire from the layer of channel material and the layer of sacrificial material, and replacing the sacrificial material in the at least one nanowire by heterojunction material. A method according to embodiments of the present disclosure is advantageous as it enables easy manufacturing of complementary TFETs.
    Type: Application
    Filed: April 8, 2011
    Publication date: October 20, 2011
    Applicants: Katholieke Universiteit Leuven, K.U. LEUVEN R&D, IMEC
    Inventors: Rita Rooyackers, Daniele Leonelli, Anne Vandooren, Anne S. Verhulst, Roger Loo, Stefan De Gendt