Abstract: A method of operating a radio transmitter configured to transmit at least one sequence of logic values by transmitting transmission signals selected in a constellation diagram having a certain cardinality comprises selecting said transmission signals out of a first subset of transmission signals in said constellation diagram, said first subset comprising a first number of transmission signals, and a second subset of transmission signals in said constellation diagram, said second subset comprising a second number of transmission signals, wherein. The transmission signals in the second subset of transmission signals have an energy higher than the transmission signals in the first subset of transmission signals. The sum of said first number of transmission signals and said second number of transmission signals is less than said cardinality.

Abstract: A system, such as, e.g., a multiplier, for processing digital signals by using digital signals in the Canonic Signed Digit representation, the system including an input element to make the digital signals available in the Binary Canonic Signed Digit representation, a converter to convert the digital signals into Canonic Signed Digit representation for use in processing. The input element may be a memory where the signals are stored in the Binary Canonic Signed Digit representation. Alternatively, the input element is adapted to be fed with digital signals in the two's complement representation, and includes at least one converter to convert the digital signals from the two's complement representation into the Binary Canonic Signed Digit representation. This preferably occurs via the T2I transformation, which leads to generating signals in the Canonic Signed Digit representation, which are then converted to the Binary Canonic Signed Digit representation.

Abstract: A data processor unit includes at least two operation-execution units, each one adapted to receive input data, perform a respective operation on the input data and outputting output data resulting after applying said operation; the data processor unit further includes: a data storage unit including at least two individually-accessible memory devices adapted to store data; a programmable controller adapted to be programmed so as to execute a selected program; a first data routing circuit arrangement adapted to receive data from the at least two memory devices, from the programmable controller and from a second data routing circuit arrangement, and for selectively routing selected ones among the received data to the input of the operation-execution units; the second data routing circuit arrangement is adapted to receive the output data outputted by the operation-execution units and to selectively route the output data to the at least two memory devices, to the programmable controller, and to the first data rout

Abstract: To generate the main scrambling code of order N and the secondary scrambling code of order K within the set identified by the primary scrambling code of order N, a first m-sequence and a second m-sequence are generated using Fibonacci linear feedback shift registers. The first m-sequence and the second m-sequence are modulo-2 added to form the I branch of the primary scrambling code. A first T-bit masking word and a second T-bit masking word of rank 0 are generated that correspond to the polynomial time shifts, and the intermediate taps of the X and y registers respectively chosen by the masking words are modulo-2 added so as to generate a third sequence and a fourth sequence, which are modulo-2 added together to form the Q branch of the primary scrambling code.

Abstract: A method for incrementing, decrementing or two's complementing a first string of bits includes generating an auxiliary string of bits as a function of the first string, and logically combining the auxiliary string with the first string to generate a corresponding output string. A least significant bit of the auxiliary string is independent from the bits of the first string, and any other bit of the auxiliary string. The method is particularly convenient for generating an overflow flag when the number to be output exceeds the representation interval. An overflow flag is generated by logically combining the most significant bits of the first and auxiliary strings.

Abstract: Described herein is a method for parallel generating Walsh-Hadamard (WH) channelization codes and Orthogonal Variable Spreading Factor (OVSF) channelization codes, which are channelization codes formed by a plurality of strings of antipodal digits, each having a given length L and being identifiable by respective indices I formed by strings of binary digits, each having a given length N equal to the logarithm in base two of the length L of the channelization codes, the antipodal digits of the channelization codes assuming the values +1 and ?1 and the binary digits of said indices I assuming the values 0 and 1.

Abstract: A data processor unit includes at least two operation-execution units, each one adapted to receive input data, perform a respective operation on the input data and outputting output data resulting after applying said operation; the data processor unit further includes: a data storage unit including at least two individually-accessible memory devices adapted to store data; a programmable controller adapted to be programmed so as to execute a selected program; a first data routing circuit arrangement adapted to receive data from the at least two memory devices, from the programmable controller and from a second data routing circuit arrangement, and for selectively routing selected ones among the received data to the input of the operation-execution units; the second data routing circuit arrangement is adapted to receive the output data outputted by the operation-execution units and to selectively route the output data to the at least two memory devices, to the programmable controller, and to the first data rout

Abstract: A system, such as, e.g., a multiplier, for processing digital signals by using digital signals in the Canonic Signed Digit representation, the system including an input element to make the digital signals available in the Binary Canonic Signed Digit representation, a converter to convert the digital signals into Canonic Signed Digit representation for use in processing. The input element may be a memory where the signals are stored in the Binary Canonic Signed Digit representation. Alternatively, the input element is adapted to be fed with digital signals in the two's complement representation, and includes at least one converter to convert the digital signals from the two's complement representation into the Binary Canonic Signed Digit representation. This preferably occurs via the T2I transformation, which leads to generating signals in the Canonic Signed Digit representation, which are then converted to the Binary Canonic Signed Digit representation.

Abstract: Described herein is a method for parallel generating Walsh-Hadamard (WH) channelization codes and Orthogonal Variable Spreading Factor (OVSF) channelization codes, which are channelization codes formed by a plurality of strings of antipodal digits, each having a given length L and being identifiable by respective indices I formed by strings of binary digits, each having a given length N equal to the logarithm in base two of the length L of the channelization codes, the antipodal digits of the channelization codes assuming the values +1 and −1 and the binary digits of said indices I assuming the values 0 and 1.

Abstract: A method for incrementing, decrementing or two's complementing a first string of bits includes generating an auxiliary string of bits as a function of the first string, and logically combining the auxiliary string with the first string to generate a corresponding output string. A least significant bit of the auxiliary string is independent from the bits of the first string, and any other bit of the auxiliary string. The method is particularly convenient for generating an overflow flag when the number to be output exceeds the representation interval. An overflow flag is generated by logically combining the most significant bits of the first and auxiliary strings.

Abstract: To generate the main scrambling code of order N and the secondary scrambling code of order K within the set identified by the primary scrambling code of order N, a first m-sequence and a second m-sequence are generated using Fibonacci linear feedback shift registers. The first m-sequence and the second m-sequence are modulo-2 added to form the I branch of the primary scrambling code. A first T-bit masking word and a second T-bit masking word of rank 0 are generated that correspond to the polynomial time shifts, and the intermediate taps of the X and y registers respectively chosen by the masking words are modulo-2 added so as to generate a third sequence and a fourth sequence, which are modulo-2 added together to form the Q branch of the primary scrambling code.