Patents by Inventor Daniele Mangano
Daniele Mangano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11906995Abstract: A voltage regulator coupled between a first node and second node includes a first (full-power) regulator circuit and a second (low-power) regulator circuit. In a first mode: the first regulator circuit is activated (with the second regulator circuit inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is kept de-activated when the voltage at the first node is a ground voltage. In a second mode: the first regulator circuitry in is active (with the second regulator circuitry inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is inactive when the voltage at the first node is a ground voltage. In a third mode: the second regulator circuitry is active (with the first regulator circuitry inactive) irrespective of the voltage at the first node being at the battery voltage or the ground voltage.Type: GrantFiled: June 9, 2022Date of Patent: February 20, 2024Assignee: STMicroelectronics S.r.l.Inventors: Daniele Mangano, Francesco Clerici, Pasquale Butta'
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Patent number: 11906994Abstract: A voltage regulator is embedded in a circuit intermediate a first node (coupled to a battery) and a second node (supplying power to an external memory). The voltage regulator is activatable in a first mode of operation for startup during which an voltage is applied to the second node that increases towards a supply threshold. In response to the voltage at the second node reaching the supply threshold, the voltage regulator transitions to a second mode of operation where a programmable regulated voltage (higher than the supply threshold) is applied to the second node. In response to receipt of a low-power operation request, a first high-drive regulator circuitry is deactivated and a second low-power regulator circuitry is activated to provide a third mode of operation at low power.Type: GrantFiled: June 9, 2022Date of Patent: February 20, 2024Assignees: STMicroelectronics S.r.l., STMicroelectronics (Rousset) SASInventors: Daniele Mangano, Andrei Tudose, Francesco Clerici, Pasquale Butta'
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Patent number: 11803226Abstract: A power-saving system includes a retention memory element for a retained peripheral that is set to a logic state during an operational-power mode and maintains the logic state during an enhanced power-saving mode. The power-saving system also includes a non-retention memory element for a non-retained peripheral that is set to a logic state during the operational-power mode of the power-saving system; and a controller that instructs the retention memory element to maintain its logic state while in an enhanced power-saving mode.Type: GrantFiled: May 14, 2020Date of Patent: October 31, 2023Assignee: STMicroelectronics S.r.l.Inventors: Daniele Mangano, Michele Alessandro Carrano, Pasquale Butta′, Sergio Abenda
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Patent number: 11764731Abstract: The present disclosure relates to an electronic device comprising a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.Type: GrantFiled: November 29, 2022Date of Patent: September 19, 2023Assignees: STMicroelectronics (Alps) SAS, STMicroelectronics (Rousset) SAS, STMicroelectronics S.r.l., STMicroelectronics (Grenoble 2) SASInventors: Benoit Marchand, Hamilton Emmanuel Querino De Carvalho, Achraf Dhayni, Daniele Mangano
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Patent number: 11705904Abstract: A microcontroller includes an input pin and internal pull-up and pull-down circuits. External pull-up and pull-down circuits are also coupled to the input pin. The microcontroller is operable according to different configuration modes which include configuring the input pin in a floating state. A control logic then configures the internal pull-up and pull-down circuits according to an internal pull-up mode to acquire a first input voltage signal (at a first logic value) from the input pin, and further configure the internal pull-up and pull-down circuits according to an internal pull-down mode to acquire a second input voltage signal (at a second logic value) from the input pin. A selection of the operating mode of the MCU is then made based on the acquired first and second logic values.Type: GrantFiled: February 15, 2022Date of Patent: July 18, 2023Assignee: STMicroelectronics S.r.l.Inventors: Daniele Mangano, Alessandro Inglese
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Patent number: 11703897Abstract: In an embodiment, a method includes: receiving a main supply voltage; generating a first regulated output voltage with a DC-DC converter; providing the main supply voltage to a driver of a control terminal of an output transistor of an LDO; receiving, at an input terminal of the LDO, the first regulated output voltage; generating, at an output terminal of the LDO, a second regulated output voltage from the first regulated output voltage; and when the main supply voltage falls below a predetermined threshold, discharging a capacitor coupled to the input terminal of the LDO by activating a switch coupled to the input terminal of the LDO.Type: GrantFiled: March 5, 2020Date of Patent: July 18, 2023Assignees: STMicroelectronics S.r.l., STMicroelectronics (Rousset) SASInventors: Michel Cuenca, Bruno Gailhard, Daniele Mangano
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Patent number: 11644504Abstract: In accordance with an embodiment, a system includes an oscillator equipped circuit having an oscillator control circuit configured to be coupled to an external oscillator and a processing unit comprising a clock controller. The clock controller includes an interface circuit configured to exchange handshake signals with the oscillator control circuit, a security circuit configured to receive the external oscillator clock signal and configured to select the external oscillator clock signal as the system clock, and a detection block configured to detect a failure in the external oscillator clock signal. Upon detection of the failure, a different clock signal is selected as the system clock and the interface circuit to interrupts a propagation of the external oscillator.Type: GrantFiled: February 14, 2020Date of Patent: May 9, 2023Assignee: STMicroelectronics S.r.l.Inventors: Mirko Dondini, Daniele Mangano, Salvatore Pisasale
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Publication number: 20230087239Abstract: The present disclosure relates to an electronic device comprising a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.Type: ApplicationFiled: November 29, 2022Publication date: March 23, 2023Inventors: Benoit Marchand, Hamilton Emmanuel Querino De Carvalho, Achraf Dhayni, Daniele Mangano
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Patent number: 11543842Abstract: An integrated circuit includes a clock control circuit coupled to a reference clock signal node and a plurality of circuits including a voltage regulator, a digital circuit, and an analog circuit. The voltage regulator, in operation, supplies a regulated voltage. The clock control circuit, in operation, generates a system clock. Input/output interface circuitry is coupled to the plurality of circuits and a common input/output node. The input/output interface circuitry, in operation, selectively couples one of the plurality of circuits to the common input/output node.Type: GrantFiled: February 27, 2020Date of Patent: January 3, 2023Assignee: STMICROELECTRONICS S.r.l.Inventors: Mirko Dondini, Daniele Mangano, Riccardo Condorelli
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Patent number: 11533019Abstract: The present disclosure relates to an electronic device comprising a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.Type: GrantFiled: February 20, 2021Date of Patent: December 20, 2022Assignees: STMicroelectronics (Alps) SAS, STMicroelectronics (Rousset) SAS, STMicroelectronics S.r.l., STMicroelectronics (Grenoble 2) SASInventors: Benoit Marchand, Hamilton Emmanuel Querino De Carvalho, Achraf Dhayni, Daniele Mangano
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Publication number: 20220397923Abstract: A voltage regulator is embedded in a circuit intermediate a first node (coupled to a battery) and a second node (supplying power to an external memory). The voltage regulator is activatable in a first mode of operation for startup during which an voltage is applied to the second node that increases towards a supply threshold. In response to the voltage at the second node reaching the supply threshold, the voltage regulator transitions to a second mode of operation where a programmable regulated voltage (higher than the supply threshold) is applied to the second node. In response to receipt of a low-power operation request, a first high-drive regulator circuitry is deactivated and a second low-power regulator circuitry is activated to provide a third mode of operation at low power.Type: ApplicationFiled: June 9, 2022Publication date: December 15, 2022Applicants: STMicroelectronics S.r.l., STMicroelectronics (Rousset) SASInventors: Daniele MANGANO, Andrei TUDOSE, Francesco CLERICI, Pasquale BUTTA'
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Publication number: 20220397924Abstract: A voltage regulator coupled between a first node and second node includes a first (full-power) regulator circuit and a second (low-power) regulator circuit. In a first mode: the first regulator circuit is activated (with the second regulator circuit inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is kept de-activated when the voltage at the first node is a ground voltage. In a second mode: the first regulator circuitry in is active (with the second regulator circuitry inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is inactive when the voltage at the first node is a ground voltage. In a third mode: the second regulator circuitry is active (with the first regulator circuitry inactive) irrespective of the voltage at the first node being at the battery voltage or the ground voltage.Type: ApplicationFiled: June 9, 2022Publication date: December 15, 2022Applicant: STMicroelectronics S.r.l.Inventors: Daniele MANGANO, Francesco CLERICI, Pasquale BUTTA'
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Patent number: 11496170Abstract: The present disclosure relates to a method for controlling a device comprising an oscillation circuit, configured to provide a clock signal to a radio frequency circuit, and an antenna, in which the enabling of the passage of the signal from the circuit to the antenna is delayed with respect to an instant from which a power amplifier of the circuit is enabled.Type: GrantFiled: February 20, 2021Date of Patent: November 8, 2022Assignees: STMicroelectronics (Alps) SAS, STMicroelectronics S.r.l., STMicroelectronics (Grenoble 2) SASInventors: Benoit Marchand, Hamilton Emmanuel Querino De Carvalho, Daniele Mangano, Santo Leotta
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Publication number: 20220263509Abstract: A microcontroller includes an input pin and internal pull-up and pull-down circuits. External pull-up and pull-down circuits are also coupled to the input pin. The microcontroller is operable according to different configuration modes which include configuring the input pin in a floating state. A control logic then configures the internal pull-up and pull-down circuits according to an internal pull-up mode to acquire a first input voltage signal (at a first logic value) from the input pin, and further configure the internal pull-up and pull-down circuits according to an internal pull-down mode to acquire a second input voltage signal (at a second logic value) from the input pin. A selection of the operating mode of the MCU is then made based on the acquired first and second logic values.Type: ApplicationFiled: February 15, 2022Publication date: August 18, 2022Applicant: STMicroelectronics S.r.l.Inventors: Daniele MANGANO, Alessandro INGLESE
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Patent number: 11239796Abstract: An embodiment of the present disclosure relates to a device comprising an electronic circuit; an oscillation circuit comprising a quartz crystal, configured to provide a clock signal to the electronic circuit; and a heater configured to increase the temperature of the quartz crystal.Type: GrantFiled: February 20, 2021Date of Patent: February 1, 2022Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS (GRENOBLE 2) SASInventors: Daniele Mangano, Benoit Marchand, Santo Leotta, Hamilton Emmanuel Querino De Carvalho
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Publication number: 20210357015Abstract: A power-saving system includes a retention memory element for a retained peripheral that is set to a logic state during an operational-power mode and maintains the logic state during an enhanced power-saving mode. The power-saving system also includes a non-retention memory element for a non-retained peripheral that is set to a logic state during the operational-power mode of the power-saving system; and a controller that instructs the retention memory element to maintain its logic state while in an enhanced power-saving mode.Type: ApplicationFiled: May 14, 2020Publication date: November 18, 2021Inventors: Daniele Mangano, Michele Alessandro Carrano, Pasquale Butta', Sergio Abenda
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Publication number: 20210278868Abstract: In an embodiment, a method includes: receiving a main supply voltage; generating a first regulated output voltage with a DC-DC converter; providing the main supply voltage to a driver of a control terminal of an output transistor of an LDO; receiving, at an input terminal of the LDO, the first regulated output voltage; generating, at an output terminal of the LDO, a second regulated output voltage from the first regulated output voltage; and when the main supply voltage falls below a predetermined threshold, discharging a capacitor coupled to the input terminal of the LDO by activating a switch coupled to the input terminal of the LDO.Type: ApplicationFiled: March 5, 2020Publication date: September 9, 2021Inventors: Michel Cuenca, Bruno Gailhard, Daniele Mangano
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Publication number: 20210265949Abstract: An embodiment of the present disclosure relates to a device comprising an electronic circuit; an oscillation circuit comprising a quartz crystal, configured to provide a clock signal to the electronic circuit; and a heater configured to increase the temperature of the quartz crystal.Type: ApplicationFiled: February 20, 2021Publication date: August 26, 2021Inventors: Daniele Mangano, Benoit Marchand, Santo Leotta, Hamilton Emmanuel Querino De Carvalho
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Publication number: 20210265950Abstract: The present disclosure relates to an electronic device comprising a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.Type: ApplicationFiled: February 20, 2021Publication date: August 26, 2021Inventors: Benoit Marchand, Hamilton Emmanuel Querino De Carvalho, Achraf Dhayni, Daniele Mangano
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Publication number: 20210266024Abstract: The present disclosure relates to a method for controlling a device comprising an oscillation circuit, configured to provide a clock signal to a radio frequency circuit, and an antenna, in which the enabling of the passage of the signal from the circuit to the antenna is delayed with respect to an instant from which a power amplifier of the circuit is enabled.Type: ApplicationFiled: February 20, 2021Publication date: August 26, 2021Inventors: Benoit Marchand, Hamilton Emmanuel Querino De Carvalho, Daniele Mangano, Santo Leotta