Abstract: A method for managing a queue, such as for example a FIFO queue, and executing a look-ahead function on the data contained in the queue includes associating to the data in the queue respective state variables (C1, C2, . . . CK), the value of each of which represents the number of times a datum is present in the queue. The look-ahead function is then executed on the respective state variables, preferentially using a number of state variables (C1, C2, . . . CK) equal to the number of different values that may be assumed by the data in the queue. The look-ahead function can involve identification of the presence of a given datum in the queue and is, in that case, executed by verifying whether among the state variables (C1, C2, . . . CK) there exists a corresponding state variable with non-nil value.

Abstract: Full-duplex communication over a communication link between an initiator operating with an initiator clock and a target operating with a target clock involves, in communication from the initiator to the target: storing data from the initiator in a first FIFO memory with the initiator clock, reading data from the initiator stored in the first FIFO memory, wherein reading is with the target clock transmitting the data read from the first FIFO memory over a first mesochronous link, and storing the data transmitted over the first mesochronous link in a buffer whereby the data are made available to the target. Communication from the target to the initiator includes: transmitting data from the target over a second mesochronous link, and storing the data transmitted over the second mesochronous link in a second FIFO memory, wherein storing is with the target clock, whereby the data are made available to the initiator for reading from the second FIFO memory with the initiator clock signal.

Abstract: A system such as a “System-on-Chip” includes an interconnection network, a set of initiator modules for transmitting data towards the interconnection network and at least one communication arbiter for deciding, as a function of a set of configuration values, which transmissions of the initiator modules have access to the interconnection network. At least one configuration value is associated with each initiator module. A control device coupled to at least one of the initiator modules detects a communication status associated with the transmissions of the coupled initiator and generates a communication status signal whose value is representative of such status, determines a filtered value representative of a series of the values of the communication status signal, and selectively varies one of the configuration values as a function of the filtered value.

Abstract: Data transport is provided in a communication network such as a Network-on-Chip arrangement via full-duplex mesochronous links between routers. Request signals and response signals are exchanged between these routers acting alternatively as an initiator and a target operating in respective clock domains at opposite ends of respective full-duplex mesochronous links. The request initiator flow control signals are monitored at the target end of the link while the response target flow control signals are monitored at the initiator end of the link. The monitoring action involves ascertaining if a request has been granted at the initiator end of the link and if a response has been granted at the target end of said link thus correspondingly managing the data flow over the link.

Abstract: A method of performing transactions in a communication network in which is exchanged between Intellectual Property (IP) cores has information transported in packets which include a header for transporting control information and one or more payloads transporting content. A versatile packet format is used which is adapted to transport different traffic patterns generated by the IP cores using different protocols for simple interoperability between the IP cores and also providing configurability of the granularity arbitration process to correct crossing the routers in the communication network.

Abstract: A synchronization system to synchronize modules (TX, RX) in an integrated circuit, such as a VLSI integrated circuit, in which the modules receive respective first and second clock signals (TX_CLK, RX_CLK) having a same frequency but being shifted by a constant and unknown phase difference. The system includes a first latch means for latching and delivering data in synchronism with the first clock signal and second latch means for latching data issued from the first latch means and delivering data in synchronism with the second clock signal, first and second latch means being controlled by first and second control signals (strobe_W, strobe_R) elaborated respectively from said first and second clock signals and one of said first and second control signal being shifted by an amount corresponding at least to the set-up time of at least one of said first and second latch means.

Abstract: Full-duplex communication over a communication link between an initiator operating with an initiator clock and a target operating with a target clock involves, in communication from the initiator to the target: storing data from the initiator in a first FIFO memory with the initiator clock, reading data from the initiator stored in the first FIFO memory, wherein reading is with the target clock transmitting the data read from the first FIFO memory over a first mesochronous link, and storing the data transmitted over the first mesochronous link in a buffer whereby the data are made available to the target. Communication from the target to the initiator includes: transmitting data from the target over a second mesochronous link, and storing the data transmitted over the second mesochronous link in a second FIFO memory, wherein storing is with the target clock, whereby the data are made available to the initiator for reading from the second FIFO memory with the initiator clock signal.

Abstract: Data transport is provided in a communication network such as a Network-on-Chip arrangement via full-duplex mesochronous links between routers. Request signals and response signals are exchanged between these routers acting alternatively as an initiator and a target operating in respective clock domains at opposite ends of respective full-duplex mesochronous links. The request initiator flow control signals are monitored at the target end of the link while the response target flow control signals are monitored at the initiator end of the link. The monitoring action involves ascertaining if a request has been granted at the initiator end of the link and if a response has been granted at the target end of said link thus correspondingly managing the data flow over the link.

Abstract: A synchronization system to synchronize modules (TX, RX) in an integrated circuit, such as a VLSI integrated circuit, in which the modules receive respective first and second clock signals (TX_CLK, RX_CLK) having a same frequency but being shifted by a constant and unknown phase difference. The system includes a first latch means for latching and delivering data in synchronism with the first clock signal and second latch means for latching data issued from the first latch means and delivering data in synchronism with the second clock signal, first and second latch means being controlled by first and second control signals (strobe_W, strobe_R) elaborated respectively from said first and second clock signals and one of said first and second control signal being shifted by an amount corresponding at least to the set-up time of at least one of said first and second latch means.

Abstract: A decoupler that allows for asynchronous communication between two synchronous IP cores. The decoupler reduces or eliminates the need for distribution and balancing of the clock. More specifically, the decoupler provides the ability to decouple an IP core from the interconnect clock domain, thereby reducing the need for clock balancing. The decoupler is inserted between a source IP core and a target IP core, and may include two interfaces, one located near the source and another located near the target. Synchronous data messages are converted to asynchronous data messages for transmission across a physical connection. Once the asynchronous data message is received by the interface near the target or source, the data message is converted back to a synchronous message.