Abstract: Systems and methods related to a memory device that includes a command interface configured to receive read commands and write commands to invoke read and write operations. The memory device also includes a memory bank having multiple memory cells implemented using ferroelectric layers between plate lines and digit lines. The memory device also includes bank control circuitry configured to control operation of the memory bank. The operation of the memory bank includes programming both high and low logic values as a write back to the multiple memory cells during a read and write phase where the read and write operations are performed after sensing values from the multiple memory cells.

Abstract: Methods, systems, and devices for memory operations are described. First scrambling sequences may be generated for first addresses of a memory device after an occurrence of a first event, where the first addresses may be associated with commands received at the memory device. Portions of the memory array corresponding to the first address may be accessed based on the first scrambling sequences. After an occurrence of a subsequent event, second scrambling sequences may be generated for the first addresses, where the second scrambling sequences may be different than the first set of scrambling sequences. After the occurrence of the subsequent event, the portions of the memory array may be accessed based on the second scrambling sequences.

Abstract: Methods, systems, and devices for storing bits, such as N?1 bits, with cells, such as N cells, in a memory device are described. A memory device may generate a first sensing voltage that is based on a first voltage of a first digit line and a second voltage of a second digit line. The memory device may also generate a second sensing voltage that is based on a third voltage of a third digit line and a fourth voltage of a fourth digit line. The memory device may then determine a bit value based at least in part on a difference between the first sensing voltage and the second sensing voltage.

Abstract: Systems and methods are related to a memory device including a plate line. The memory device also includes a pair of ferroelectric layers implementing a pair of memory cells and coupled to opposite sides of the plate line. The memory device further includes a pair of digit lines each coupled to a respective ferroelectric layer of the pair of ferroelectric layers. The memory device also includes a sense amplifier coupled to the pair of digit lines and configured to sense and amplify voltages received at the digit lines from the respective memory cells. The sense amplifier includes a threshold voltage compensated latch that includes multiple p-channel transistors and is configured to compensate for process, voltage, or temperature variation mismatches between the threshold voltages of the multiple p-channel transistors.

Abstract: Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation associated with a memory cell. The method includes precharging a first side and a second side of a latch stage of the sense component to the first voltage based on precharging the output of the amplifier stage to the first voltage, the latch stage coupled with the amplifier stage. The method may also include coupling a second voltage from a digit line associated with the memory cell to the input of the amplifier stage, the amplifier stage generating a third voltage on the output based on coupling the second voltage to the input, and the latch stage latching a logic value associated with the memory cell based on the third voltage.

Abstract: Methods, systems, and devices for data masking for memory are described. A memory device may set multiple data masking flags for associated memory array(s) at power-up. Each data masking flag may be associated with a respective page of memory cells and may indicate whether the data stored in the respective page is masked data, or whether the data is new, unmasked data. Data existing at a previous power-down may be masked until an initial write or activate command has been performed on the page after power-up, where the initial write or activate command may result in writing masked data, write data, or a combination thereof to the page. After previously stored data is overwritten to a page, the flag associated with the page may be reset, which may indicate that data stored at the page is available to be read.

Abstract: The present disclosure includes apparatuses, methods, and systems for adjusting a sensing voltage in memory. An embodiment includes a memory having a group of memory cells, wherein a sub-group of the memory cells of the group remain programmed to a same data state, and circuitry configured to determine an amount of charge associated with the memory cells of the sub-group and adjust a voltage used to sense a data state of the memory cells of the group based, at least in part, on the determined amount of charge.

Abstract: Systems and methods are related to a memory device including a plate line. The memory device also includes a pair of ferroelectric layers implementing a pair of memory cells and coupled to opposite sides of the plate line. The memory device further includes a pair of digit lines each coupled to a respective ferroelectric layer of the pair of ferroelectric layers. The memory device also includes a sense amplifier coupled to the pair of digit lines and configured to sense and amplify voltages received at the digit lines from the respective memory cells. The sense amplifier includes a threshold voltage compensated latch that includes multiple p-channel transistors and is configured to compensate for process, voltage, or temperature variation mismatches between the threshold voltages of the multiple p-channel transistors.

Abstract: Methods, systems, and devices for memory array with multiplexed select lines are described. In some cases, a memory cell of the memory device may include a storage component, a first transistor coupled with a word line, and a second transistor coupled with a first select line to selectively couple the memory cell with a first digit line. A third transistor may be coupled with the first digit line and a sense component common to a set of digit lines and a set of select lines. A second select line may be coupled with the third transistor and configured to couple the sense component with the first digit line and to couple the sense component with a second digit line. The sense component may determine a logic state stored by the memory cell based on the signal from the first digit line and the signal from the second digit line.

Abstract: Methods, systems, and devices for memory array configuration for shared word lines are described. A memory array of a memory device may include shared (e.g., shorted) word lines. The memory array may include multiple memory cells, word lines, rows of transistors, and digit lines. Each transistor of the rows of transistors may be coupled with a respective memory cell and includes a connection between a first word line, a second word line, and a gate terminal of a transistor. Additionally, each digit line may be coupled with respective terminals of respective transistors of alternating rows of transistors including a first subset of alternating rows and a second subset of alternating rows that are exclusive from each other. The transistors may be configured according to a first configuration including two digit lines overlapping each transistor or a second configuration including a single digit line overlapping each transistor.

Abstract: Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation associated with a memory cell. The method includes precharging a first side and a second side of a latch stage of the sense component to the first voltage based on precharging the output of the amplifier stage to the first voltage, the latch stage coupled with the amplifier stage. The method may also include coupling a second voltage from a digit line associated with the memory cell to the input of the amplifier stage, the amplifier stage generating a third voltage on the output based on coupling the second voltage to the input, and the latch stage latching a logic value associated with the memory cell based on the third voltage.

Abstract: A method of performing a memory cell operation can include maintaining a plate voltage at a first access line of a memory cell during at least a first operation and a second operation of the memory cell. The method can further include charging a second access line to a first voltage greater than zero and greater than a threshold voltage of a selector device of the memory cell during the first operation on the memory cell. The method can further include, subsequent to the first operation, charging the second access line to a second voltage greater than the plate voltage plus the threshold voltage of the selector device to perform the second operation of the memory cell.

Abstract: Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.

Abstract: Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.

Abstract: Techniques and configurations for electronic memory are described. An apparatus may include a first set of memory cells coupled with a first plate line and a word line, where a memory cell in the first set of memory cells may be coupled with a first bit line, and a second set of memory cells coupled with a second plate line and the word line, where a memory cell of the second set of memory cells may be coupled with a second bit line. The apparatus may also include a sense component having a first node coupled with the first bit line and a first capacitor and a second node coupled with the second bit line and a second capacitor. Also, a set of capacitors may be coupled with both nodes. The capacitors may support adjustment of the voltage of the nodes of the sense component.

Abstract: Methods, systems, and devices for data masking for memory are described. A memory device may set multiple data masking flags for associated memory array(s) at power-up. Each data masking flag may be associated with a respective page of memory cells and may indicate whether the data stored in the respective page is masked data, or whether the data is new, unmasked data. Data existing at a previous power-down may be masked until an initial write or activate command has been performed on the page after power-up, where the initial write or activate command may result in writing masked data, write data, or a combination thereof to the page. After previously stored data is overwritten to a page, the flag associated with the page may be reset, which may indicate that data stored at the page is available to be read.

Abstract: Methods, systems, and devices for signal development circuitry layouts in a memory device are described. A memory device may include signal development circuitry that is positioned in multiple levels of a memory die relative to a substrate. For example, a set of first transistors used for developing access signals may be located on a first level of a memory die, and a set of second transistors used for developing the access signals may be located on a second level of the memory die. Formation of the set of first transistors and the set of second transistors may involve processing operations that are common with the formation of other transistors on a respective level, such as cell selection transistors, deck selection transistors, shunting transistors, and other transistors of the respective level.

Abstract: Methods, systems, and devices for a sensing scheme that extracts the full or nearly full remnant polarization charge difference between two logic states of a ferroelectric memory cell or cells is described. The scheme employs a charge mirror to extract the full charge difference between the two states of a selected memory cell. The charge mirror may transfer the memory cell polarization charge to an amplification capacitor. The signal on the amplification capacitor may then be compared with a reference voltage to detect the logic state of the memory cell.

Abstract: The present disclosure includes apparatuses, methods, and systems for preventing parasitic current during program operations in memory. An embodiment includes a sense line, an access line, and a memory cell. The memory cell includes a first transistor having a floating gate and a control gate, wherein the control gate of the first transistor is coupled to the access line, and a second transistor having a control gate, wherein the control gate of the second transistor is coupled to the access line, a first node of the second transistor is coupled to the sense line, and a second node of the second transistor is coupled to the floating gate of the first transistor. The memory cell also includes a diode, or other rectifying element, coupled to the sense line and a node of the first transistor.

Abstract: Devices and methods for operating a memory device including multiple memory cells configured to store data and multiple global digit lines configured to carry the data in memory accesses of the memory cells. The memory device also includes multiple local digit lines configured to carry the data between the global digit lines and the memory cells. The memory device further includes multiple digit line selection circuits configured to selectively couple selected local digit lines of the local digit lines to the global digit lines. The memory device also includes a controller configured to select a pattern of selected digit line selection circuits to at least partially cancel capacitive coupling between the selected local digit lines.