Abstract: A method of transferring data in a processing system comprising a shared memory for storing data blocks, a plurality of processors, at least one of the processors having a cache memory for the data blocks, a plurality of data buses to each one at least one processor is connected, cross-bar for selectively connecting the data buses and the shared memory therebetween; the method comprises the steps of requesting the reading of a data block from the shared memory by a requesting processor, if the requested data block is present in modified form in the cache memory of an intervening processor, requesting an access to the corresponding data bus by the intervening processor, granting the access to the intervening processor, and to any other data bus available to the cross-bar, and sending the modified data block onto the data bus corresponding to the intervening processor and then onto the other data buses available.

Abstract: A method of transferring data in a processing system comprising a shared memory for storing data blocks, a plurality of processors, at least one of the processors having a cache memory for the data blocks, a plurality of data buses to each one at least one processor is connected, cross-bar means for selectively connecting the data buses and the shared memory therebetween; the method comprises the steps of requesting the reading of a data block from the shared memory by a requesting processor, if the requested data block is present in modified form in the cache memory of an intervening processor, requesting an access to the corresponding data bus by the intervening processor, granting the access to the intervening processor, granting an access to any other data bus available to the cross-bar means, logically connecting the data bus corresponding to the intervening processor with the other data buses available, and sending the modified data block onto the data bus corresponding to the intervening processor and

Abstract: A memory having variable interleaving levels and associated configurator circuit which provides for the optimum level of interleaving based on the memory configuration. A number of independently addressable storage modules may be installed in the memory, the modules having various capacities which are usually multiples of a basic capacity. The configurator circuit receives a first field (ALOW) of least significant bits from the address for the desired memory entry and a second field (AHIGH) of bits of greater weight from the memory address. According to the number of the modules present in the memory and their capacities, the configurator circuit generates a module selection signal for selecting from the various modules present and a plurality of signals (MBIT) representing the memory module address bits. The configurator circuit thereby configures the memory with the highest levels of interleaving allowed by the capacity of the modules installed and properly addresses the selected module.

Abstract: In a multiprocessor system having global data replication in each of the local memories, each associated with one of the processors, the global data allocation in the several local memories is performed by translating global data logical addresses into addresses conventionally defined as real, the translation being performed by a first translation unit associated with and managed by the processor which generates the global data. The first translation is followed by the translation of the real address into a physical address generally differing for each local memory and performed by a plurality of translation units, each associated with one of the local memories and managed by the processor associated with that local memory.

Abstract: A memory module selection and reconfiguration apparatus in a data processing system wherein a modular working memory formed by a plurality of memory modules sends to a central processing unit information related to the capacities of the constituting modules (M1, M2, M3, M4) during the system initialization. The central unit processes such information and provides memory, via a channel (30), with information representative of the capacity of the first modules (G1), of the sum of the capacities of the first and second module (G2), of the sum of the capacities of the first, second and third module (G3) and so on, up to the total capacity of the working memory. This information is stored into registers (31, 32), each one related to a possible module, of a module selection unit included inside the working memory.

Abstract: A digital timing unit for timing a data processing system or units thereof, wherein the output signals of a shift register are applied to a plurality of EXCLUSIVE OR gates (G.sub.1) . . . (G.sub.n). The shift register is activated from a known state so that an electric transition signal is shifted through the register cells. A timing cycle is thus defined which is utilized to set the register in a second known state. Feedback and control logic are provided for activating the register independently of its state and keeping it in the state occurring at the end of a timing cycle until a new start signal is received. Shifting of the register is caused by timing pulses generated by an oscillator (1). The timing signals generated by the timing unit and present on the output terminals of the EXCLUSIVE OR may be modified, as to the length, by changing the oscillator period and/or the connection between the EXCLUSIVE OR inputs and the outputs of the shift register.