Patents by Inventor Danielle A. Thomas
Danielle A. Thomas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240237991Abstract: A junctional tourniquet apparatus and related methods of use. An exemplary tourniquet has an inverted cone shape, wherein a narrower end has a mushroom shaped base that is pressed against a compression target and a broader end has a plurality of pass-through slots for straps. Another exemplary tourniquet has a broad plate component and a handle component. The handle component has a mushroom shaped base on a first end and a handle on a second end. The handle component passes through the center of the plate component with threads that allow the handle component to compress a target by twisting the handle.Type: ApplicationFiled: February 2, 2024Publication date: July 18, 2024Applicant: The United States of America, as represented by the Secretary of the NavyInventors: Joseph Thomas Burkart, Danielle E. Cafasso, Robert Henry Hayford, Huckelberry Finne, Jose Ramirez Vargas, Michael P Abbott
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Patent number: 8633525Abstract: In capacitive sensor circuits where physical contact is required and excess pressure may be inadvertently applied to the sensor surface, aluminum is not sufficiently hard to provide “scratch” protection and may delaminate, causing circuit failure, even if passivation integrity remains intact. Because hard passivation layers alone provide insufficient scratch resistance, at least the capacitive electrodes and preferably all metallization levels within the sensor circuit in the region of the capacitive electrodes between the surface and the active regions of the substrate are formed of a conductive material having a hardness greater than that of aluminum, and at least as great as the lowest hardness for any interlevel dielectric or passivation material employed.Type: GrantFiled: September 14, 2011Date of Patent: January 21, 2014Assignee: STMicroelectronics, Inc.Inventor: Danielle A. Thomas
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Patent number: 8569809Abstract: Sensor cells are arranged in an array in an organic semiconductor layer. Row and column select circuitry addresses the cells of the array one cell at a time to determine the presence of an object, such as a fingerprint ridge or valley, contacting or proximate to a sensing surface above each cell. Control circuitry can be provided in a companion silicon chip or in a second layer of organic semiconductor material to communicate with the array and an associated system processor. The array of sensor cells can be fabricated using a flexible polymer substrate that is peeled off and disposed of after contacts have been patterned on the organic semiconductor layer. The organic semiconductor layer can be used with a superimposed reactive interface layer to detect specific chemical substances in a test medium.Type: GrantFiled: October 13, 2006Date of Patent: October 29, 2013Assignee: STMicroelectronics, Inc.Inventors: Danielle A. Thomas, Bruno J. Debeurre, Peter J. Thoma
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Patent number: 8163645Abstract: A system and method is disclosed for providing a redistribution metal layer in an integrated circuit. The redistribution metal layer is formed from the last metal layer in the integrated circuit during manufacture of the integrated circuit before final passivation is applied. The last metal layer provides sites for solder bump pads used in flip chip interconnection. The redistribution metal layer can be (1) a flat layer deposited over the next to last metal layer through an opening in a dielectric layer, or (2) deposited over an array of vias connected to the next to last metal layer. Space between the solder bump pads is deposited with narrower traces for connecting active circuit areas below. A final passivation layer is deposited to ensure product reliability.Type: GrantFiled: July 30, 2010Date of Patent: April 24, 2012Assignee: STMicroelectronics, Inc.Inventors: Danielle A. Thomas, Harry Michael Siegel, Antonio A. Do Bento Vieira, Anthony M. Chiu
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Publication number: 20120091517Abstract: In capacitive sensor circuits where physical contact is required and excess pressure may be inadvertently applied to the sensor surface, aluminum is not sufficiently hard to provide “scratch” protection and may delaminate, causing circuit failure, even if passivation integrity remains intact. Because hard passivation layers alone provide insufficient scratch resistance, at least the capacitive electrodes and preferably all metallization levels within the sensor circuit in the region of the capacitive electrodes between the surface and the active regions of the substrate are formed of a conductive material having a hardness greater than that of aluminum, and at least as great as the lowest hardness for any interlevel dielectric or passivation material employed.Type: ApplicationFiled: September 14, 2011Publication date: April 19, 2012Inventor: Danielle A. Thomas
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Patent number: 8039343Abstract: In capacitive sensor circuits where physical contact is required and excess pressure may be inadvertently applied to the sensor surface, aluminum is not sufficiently hard to provide “scratch” protection and may delaminate, causing circuit failure, even if passivation integrity remains intact. Because hard passivation layers alone provide insufficient scratch resistance, at least the capacitive electrodes and preferably all metallization levels within the sensor circuit in the region of the capacitive electrodes between the surface and the active regions of the substrate are formed of a conductive material having a hardness greater than that of aluminum. The selected conductive material preferably has a hardness which is at least as great as the lowest hardness for any interlevel dielectric or passivation material employed.Type: GrantFiled: January 8, 2010Date of Patent: October 18, 2011Assignee: STMicroelectronics, Inc.Inventor: Danielle A. Thomas
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Publication number: 20100297841Abstract: A system and method is disclosed for providing a redistribution metal layer in an integrated circuit. The redistribution metal layer is formed from the last metal layer in the integrated circuit during manufacture of the integrated circuit before final passivation is applied. The last metal layer provides sites for solder bump pads used in flip chip interconnection. The redistribution metal layer can be (1) a flat layer deposited over the next to last metal layer through an opening in a dielectric layer, or (2) deposited over an array of vias connected to the next to last metal layer. Space between the solder bump pads is deposited with narrower traces for connecting active circuit areas below. A final passivation layer is deposited to ensure product reliability.Type: ApplicationFiled: July 30, 2010Publication date: November 25, 2010Inventors: Danielle A. Thomas, Harry Michael Siegel, Antonio A. Do Bento Vieira, Anthony M. Chiu
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Patent number: 7786582Abstract: A system and method is disclosed for providing a redistribution metal layer in an integrated circuit. The redistribution metal layer is formed from the last metal layer in the integrated circuit during manufacture of the integrated circuit before final passivation is applied. The last metal layer provides sites for solder bump pads used in flip chip interconnection. The redistribution metal layer can be (1) a flat layer deposited over the next to last metal layer through an opening in a dielectric layer, or (2) deposited over an array of vias connected to the next to last metal layer. Space between the solder bump pads is deposited with narrower traces for connecting active circuit areas below. A final passivation layer is deposited to ensure product reliability.Type: GrantFiled: June 19, 2006Date of Patent: August 31, 2010Assignee: STMicroelectronics, Inc.Inventors: Danielle A. Thomas, Harry Michael Siegel, Antonio A. Do Bento Vieira, Anthony M. Chiu
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Publication number: 20100117129Abstract: In capacitive sensor circuits where physical contact is required and excess pressure may be inadvertently applied to the sensor surface, aluminum is not sufficiently hard to provide “scratch” protection and may delaminate, causing circuit failure, even if passivation integrity remains intact. Because hard passivation layers alone provide insufficient scratch resistance, at least the capacitive electrodes and preferably all metallization levels within the sensor circuit in the region of the capacitive electrodes between the surface and the active regions of the substrate are formed of a conductive material having a hardness greater than that of aluminum. The selected conductive material preferably has a hardness which is at least as great as the lowest hardness for any interlevel dielectric or passivation material employed.Type: ApplicationFiled: January 8, 2010Publication date: May 13, 2010Inventor: Danielle A. Thomas
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Patent number: 7713766Abstract: A light sensor located above an integrated circuit including a lower electrode, a heavily-doped amorphous silicon layer of a first conductivity type, and a lightly-doped amorphous silicon layer of a second conductivity type. The lightly-doped amorphous silicon layer rests on a planar surface at least above and in the vicinity of the lower electrode.Type: GrantFiled: November 21, 2008Date of Patent: May 11, 2010Assignee: STMicroelectronics S.A.Inventors: Danielle Thomas, Maurice Rivoire
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Patent number: 7687839Abstract: In capacitive sensor circuits where physical contact is required and excess pressure may be inadvertently applied to the sensor surface, aluminum is not sufficiently hard to provide “scratch” protection and may delaminate, causing circuit failure, even if passivation integrity remains intact. Because hard passivation layers alone provide insufficient scratch resistance, at least the capacitive electrodes and preferably all metallization levels within the sensor circuit in the region of the capacitive electrodes between the surface and the active regions of the substrate are formed of a conductive material having a hardness greater than that of aluminum. The selected conductive material preferably has a hardness which is at least as great as the lowest hardness for any interlevel dielectric or passivation material employed.Type: GrantFiled: January 29, 2002Date of Patent: March 30, 2010Assignee: STMicroelectronics, Inc.Inventor: Danielle A. Thomas
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Publication number: 20090075410Abstract: A light sensor located above an integrated circuit including a lower electrode, a heavily-doped amorphous silicon layer of a first conductivity type, and a lightly-doped amorphous silicon layer of a second conductivity type. The lightly-doped amorphous silicon layer rests on a planar surface at least above and in the vicinity of the lower electrode.Type: ApplicationFiled: November 21, 2008Publication date: March 19, 2009Applicant: STMicroelectronics S.A.Inventors: Danielle Thomas, Maurice Rivoire
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Patent number: 7492026Abstract: A light sensor located above an integrated circuit including a lower electrode, a heavily-doped amorphous silicon layer of a first conductivity type, and a lightly-doped amorphous silicon layer of a second conductivity type. The lightly-doped amorphous silicon layer rests on a planar surface at least above and in the vicinity of the lower electrode.Type: GrantFiled: December 30, 2005Date of Patent: February 17, 2009Assignee: STMicroelectronics S.A.Inventors: Danielle Thomas, Maurice Rivoire
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Patent number: 7339204Abstract: A contact is formed within an active region of a substrate at the edge of a die, preferably within the first metallization level in the active region of the substrate. An opening having sloped sidewalls is then etched into the back side of the substrate, exposing a portion of the active region contact. An interconnect is formed on the opening sidewall to connect the active region contact with a die contact pad on the backside surface of the substrate. The active region contact preferably spans a boundary between two die, with the opening preferably etched across the boundary to permit inter-connects on opposing sidewalls of the opening to each contact the active region contact within different die, connecting the active region contact to die contact pads on different dice. The dice are then separated along the boundary, through the active region contact which becomes two separate active region contacts.Type: GrantFiled: October 1, 2001Date of Patent: March 4, 2008Assignee: STMicroelectronics, Inc.Inventor: Danielle A. Thomas
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Patent number: 7323114Abstract: A large diameter glass wafer is pattern-etched to provide a plurality of elongated lens elements arranged side-by-side, the etching leaving small rods in place to keep the lens elements connected to the wafer during mirror processing. The etching provides curved surfaces for lenses and flat surfaces for mirrors. The mirrors are formed by selectively depositing reflective material on the flat surfaces. The reflective material may comprise an oxide, nitride, sulfide, or fluoride of a transition metal. The flat surfaces that define the mirrors are disposed at angles to the longitudinal dimension of each lens element. In use in an optical disc system, light from a laser diode is reflected by the mirrors and directed at an optical disc through a first lens. Light returns from the disc on a parallel path through a second lens, passes through the lens element, and is directed at a photodetector. The system may include an elongated base element attached to each lens element.Type: GrantFiled: October 12, 2005Date of Patent: January 29, 2008Assignee: STMicroelectronics, Inc.Inventors: Anthony M. Chiu, Danielle A. Thomas
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Publication number: 20070029583Abstract: Sensor cells are arranged in an array in an organic semiconductor layer. Row and column select circuitry addresses the cells of the array one cell at a time to determine the presence of an object, such as a fingerprint ridge or valley, contacting or proximate to a sensing surface above each cell. Control circuitry can be provided in a companion silicon chip or in a second layer of organic semiconductor material to communicate with the array and an associated system processor. The array of sensor cells can be fabricated using a flexible polymer substrate that is peeled off and disposed of after contacts have been patterned on the organic semiconductor layer. The organic semiconductor layer can be used with a superimposed reactive interface layer to detect specific chemical substances in a test medium.Type: ApplicationFiled: October 13, 2006Publication date: February 8, 2007Inventors: Danielle Thomas, Bruno Debeurre, Peter Thoma
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Patent number: 7141839Abstract: Sensor cells are arranged in an array in an organic semiconductor layer. Row and column select circuitry addresses the cells of the array one cell at a time to determine the presence of an object, such as a fingerprint ridge or valley, contacting or proximate to a sensing surface above each cell. Control circuitry can be provided in a companion silicon chip or in a second layer of organic semiconductor material to communicate with the array and an associated system processor. The array of sensor cells can be fabricated using a flexible polymer substrate that is peeled off and disposed of after contacts have been patterned on the organic semiconductor layer. The organic semiconductor layer can be used with a superimposed reactive interface layer to detect specific chemical substances in a test medium.Type: GrantFiled: December 22, 2004Date of Patent: November 28, 2006Assignee: STMicroelectronics, Inc.Inventors: Danielle A. Thomas, Bruno J. Debeurre, Peter J. Thoma
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Publication number: 20060234423Abstract: A system and method is disclosed for providing a redistribution metal layer in an integrated circuit. The redistribution metal layer is formed from the last metal layer in the integrated circuit during manufacture of the integrated circuit before final passivation is applied. The last metal layer provides sites for solder bump pads used in flip chip interconnection. The redistribution metal layer can be (1) a flat layer deposited over the next to last metal layer through an opening in a dielectric layer, or (2) deposited over an array of vias connected to the next to last metal layer. Space between the solder bump pads is deposited with narrower traces for connecting active circuit areas below. A final passivation layer is deposited to ensure product reliability.Type: ApplicationFiled: June 19, 2006Publication date: October 19, 2006Applicant: STMicroelectronics, Inc.Inventors: Danielle Thomas, Harry Siegel, Antonio Do Bento Vieira, Anthony Chiu
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Patent number: 7096581Abstract: An integrated circuit includes a portion having at least one active circuit area. The integrated circuit also includes a redistribution metal layer fabricated at least partially during fabrication of the portion of the integrated circuit. A method for fabricating an integrated circuit includes fabricating a portion of the integrated circuit, where the portion includes at least one active circuit area. The method also includes fabricating a redistribution metal layer at least partially during fabrication of the portion of the integrated circuit.Type: GrantFiled: March 6, 2002Date of Patent: August 29, 2006Assignee: STMicroelectronics, Inc.Inventors: Danielle A. Thomas, Harry Michael Siegel, Antonio A. Do Bento Vieira, Anthony M. Chiu
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Publication number: 20060145282Abstract: A light sensor located above an integrated circuit including a lower electrode, a heavily-doped amorphous silicon layer of a first conductivity type, and a lightly-doped amorphous silicon layer of a second conductivity type. The lightly-doped amorphous silicon layer rests on a planar surface at least above and in the vicinity of the lower electrode.Type: ApplicationFiled: December 30, 2005Publication date: July 6, 2006Applicant: STMicroelectronics S.A.Inventors: Danielle Thomas, Maurice Rivoire