Abstract: An apparatus can include a number of memory devices and a memory controller coupled to one or more of the number of memory devices. The memory controller can include a row hammer detector. The memory controller can be configured increment for a first time period a row counter in a first data structure and a refresh counter. The memory controller can be configured to increment for a second time period a row counter in a second data structure and the refresh counter. The memory controller can be configured to determine that a value of the refresh counter exceeds a refresh threshold and responsive to the determination that the value of the refresh counter exceeds the refresh threshold, issue a notification.

Abstract: Provided in a central controller system, is a system and method to identify and mitigate errors on a die containing mission critical logical-to-physical addressing information. The logical-to-physical (L2P) addressing information is essential for translating logical memory addresses for uncompressed data to physical addresses for compressed data. When a die containing L2P data is detected as being corrupted, the corrupted data is corrected, and all the data is moved to an uncorrupted die at a specified offset from the original address of the die.

Abstract: A variety of applications can include a memory device having dynamic page mapping with compression. The memory device can include a mapping table having an entry location to associate a virtual page with a physical address of a first stripe of data of the virtual page. The entry location can include a flag along with the physical address of the first stripe. The flag can identify data of the virtual page as being compressed or uncompressed. A controller of the memory device, responsive to the flag identifying the data of virtual page being compressed, is structured to generate a format of compressed data of the first stripe with a header. The header can include a count of additional physical addresses to store compressed data of the virtual page and the additional physical addresses. Additional apparatus, systems, and methods are disclosed.

Abstract: Systems, apparatuses, and methods related to bloom filter implementation into a controller are described. A memory device is coupled to a memory controller. The memory controller is configured to implement a counting bloom filter, increment the counting bloom filter in response to a row activate command of the memory device, determine whether a value of the counting bloom filter exceeds a threshold value, and perform an action in response to the value exceeding the threshold value.

Abstract: In some implementations, a memory system controller may receive, from a host system, a memory-access request. The memory system controller may store an identifier associated with the memory-access request in a ring-buffer structure. The memory system controller may determine whether a data structure includes an entry associated with the identifier. The memory system controller may perform one of: updating a memory-access counter stored at the entry when the data structure does include the entry, or creating the entry in the data structure and initializing the memory-access counter stored at the entry when the data structure does not include the entry. The memory system controller may receive, from the host system, a request to read the data structure and/or may transmit, to the host system and based on the request, an indication of a respective identifier and a respective memory-access counter for each entry having a respective flag set.

Abstract: A method can include performing at least one glitch resistance operation and detecting, by a circuit included in a glitch detector coupled via a connection matrix to a first processing unit, an indication of a glitch on a memory system. The method can include notifying, via the connection matrix, at least a second processing unit of the detected indication of the glitch. The method can include subsequent to notifying at least the second processing unit, transmitting via the at least the second processing unit a glitch confirmation signal.

Abstract: Implementations described herein relate to a device identifier composition engine (DICE) 3-layer architecture. In some implementations, a device may include a secure computing environment including a hardware root of trust (HRoT) DICE component. The secure computing environment may include a DICE layer 0 component configured to derive a DICE identity key. The secure computing environment may include a DICE layer 1 component configured to derive a DICE alias key based on the DICE identity key. The secure computing environment may include a controller configured to receive an update to firmware of a component. The controller may be configured to update the firmware of the component based on receiving the update. The controller may be configured to update one or more keys of the component or one or more keys of one or more components above the component in a layer stack.

Abstract: Systems, apparatuses, and methods related to data identity recognition for semiconductor devices are described. A system includes a host and a memory device coupled to the host via an interconnect bus. The host includes a host security manager configured to encrypt data of a command, perform a memory integrity check, allow access to memory of a memory device corresponding to an address of a command based on which entity associated with the host sent the command, generate security keys, program security keys into the memory device, program encryption ranges, or any combination thereof. The memory device includes a memory encryption manager and a memory device security manager. The memory device security manager is configured to detect whether a command was sent from a trusted domain of the host or non-trusted domain of the host and identify which entity associated with the host initiated the command.

Abstract: A controller can be configured to enable a host to control media testing on a memory device. The interface between the host and the memory can be abstract, such that the host does not have direct control over the memory. Instead, the controller can provide translation between a host protocol, such as compute express link (CXL), and a memory protocol, such as a protocol to control a dual data rate (DDR) interface. The controller can enable media test capability discovery, configuration, and/or control for the host. The controller can enable media test result reporting from the memory to the host.

Abstract: An electronic device can be configured to enable a host to indirectly control testing associated with the electronic device. The interface between the host and the electronic device can be abstract, such that the host does not have direct control over the electronic device. Examples of the electronic device include a memory device and a power management integrated circuit. The electronic device can allow the host to discover a quantity of tests supported by the electronic device and corresponding test descriptors. The electronic device can interact with the host to configure tests and/or reporting of test results.

Abstract: In some implementations, a memory device may configure multiple access trackers to track accesses to a memory, including a counting bloom filter access tracker associated with a first memory address range, a cache-based tracker access tracker associated with a second memory address range, and a sorted look-up table access tracker associated with a third memory address range. The memory device may receive an access request indicating a memory address to be accessed and may determine that the memory address is within at least one of the first, second, or third memory address range. The memory device may determine one or more unit identifiers associated with the memory address, may identify one or more access trackers that are associated with the one or more unit identifiers, and may update one or more counters associated with the one or more access trackers, accordingly.

Abstract: A system can include a memory device; and a processing device, operatively coupled with the memory device, to perform operations including: receiving a write command comprising first data and a first key identifier; performing a first computation on the first data and the first key identifier to generate second data; storing the second data in the memory device; and storing a parity value of the second data in the memory device.

Abstract: A method can include performing at least one glitch resistance operation and detecting, by a circuit included in a glitch detector coupled via a connection matrix to a first processing unit, an indication of a glitch on a memory system. The method can include notifying, via the connection matrix, at least a second processing unit of the detected indication of the glitch. The method can include subsequent to notifying at least the second processing unit, transmitting via the at least the second processing unit a glitch confirmation signal.

Abstract: Methods, systems, and devices for access pattern tracking are described. An access request associated with accessing first data stored in memory may be received. Based on receiving the access request, a hash value based on a page index indicated in the access request may be calculated. Based on the hash value, a counter associated with the hash value may be incremented. Based on incrementing the counter, an access pattern associated with access data in the memory may be indicated.

Abstract: Systems and methods for finite time counting period counting of infinite data streams is presented. In particular example systems and methods enable counting row accesses to a memory media device over predetermined time intervals in order to deterministically detect row hammer attacks on the memory media device. Example embodiments use two identical tables that are reset at times offset in relation to each other in a ping-pong manner in order to ensure that there exists no false negative detections. The counting techniques described in this disclosure can be used in various types of row hammer mitigation techniques and can be implemented in content addressable memory or another type of memory. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be a dynamic random access memory type device.

Abstract: Methods, systems, and devices related to field firmware update (FFU). A first memory of a memory module may receive an encrypted segment of a FW package associated with FFU. A decrypted segment of the FW package may be stored by the first memory. A re-encrypted segment of the FW package may be stored by the first memory. The re-encrypted segment of the FW package may be communicated to a second memory of the memory module.

Abstract: Implementations described herein relate to a device identifier composition engine (DICE) 3-layer architecture. In some implementations, a device may include a secure computing environment including a hardware root of trust (HRoT) DICE component. The secure computing environment may include a DICE layer 0 component configured to derive a DICE identity key. The secure computing environment may include a DICE layer 1 component configured to derive a DICE alias key based on the DICE identity key. The secure computing environment may include a controller configured to receive an update to firmware of a component. The controller may be configured to update the firmware of the component based on receiving the update. The controller may be configured to update one or more keys of the component or one or more keys of one or more components above the component in a layer stack.

Abstract: Protection for a secure boot procedure can be provided in addition to cryptographic verification of boot firmware associated with the boot procedure. While the boot firmware is being verified and executed at a secure sub-system, an open sub-system can be put into a halt state, during which the open sub-system is prevented from performing the boot procedure. The open sub-system is still prevented from performing the boot procedure even if the boot firmware is verified and/or executed unless the open sub-system is put into the resume state again.

Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

Abstract: A controller can be configured to enable a host to control media testing on a memory device. The interface between the host and the memory can be abstract, such that the host does not have direct control over the memory. Instead, the controller can provide translation between a host protocol, such as compute express link (CXL), and a memory protocol, such as a protocol to control a dual data rate (DDR) interface. The controller can enable media test capability discovery, configuration, and/or control for the host. The controller can enable media test result reporting from the memory to the host.