Abstract: A memory system can be provided with error detection capabilities at various levels and authentication and integrity check capabilities in parallel with data security schemes. The error detection capabilities can check for any errors not only on data paths within a memory controller, but also on data stored in memory devices. The authentication capabilities provided in parallel with the data security schemes can ensure/strengthen data integrity of the memory system to be compliant with standardized requirements and/or protocols, such as trusted execution engine security protocol (TSP).

Abstract: Methods, systems, and devices related to firmware validation for firmware updates are disclosed. A controller can, in association with a firmware update of a memory module: determine whether first security information and first customer information of a manifest of a firmware package are valid using second security information and second customer information, respectively, stored by a non-volatile memory device of the memory module; determine whether a first public key of a first image of the firmware package is valid using a second public key of the manifest corresponding to the first image and associated with the first security information and the first customer information; and determine whether a third public key of a second image of the firmware package is valid using a fourth public key of the manifest corresponding to the second image and associated with the first security information and the first customer information.

Abstract: The present disclosure includes apparatuses and methods for providing energy information to memory. An embodiment includes determining, by a host, that a charge level of an energy source coupled to the host has reached or exceeded a threshold value, and transmitting, from the host to a memory device coupled to the host, signaling indicative of an energy mode for the memory device, wherein the signaling is transmitted based at least in part on determining that the charge level of the energy source has reached or exceeded the threshold.

Abstract: A variety of applications can include a memory device having dynamic page mapping with compression. The memory device can include a mapping table having an entry location to associate a virtual page with a physical address of a first stripe of data of the virtual page. The entry location can include a flag along with the physical address of the first stripe. The flag can identify data of the virtual page as being compressed or uncompressed. A controller of the memory device, responsive to the flag identifying the data of virtual page being compressed, is structured to generate a format of compressed data of the first stripe with a header. The header can include a count of additional physical addresses to store compressed data of the virtual page and the additional physical addresses. Additional apparatus, systems, and methods are disclosed.

Abstract: Systems, apparatuses, and methods related to data identity recognition for semiconductor devices are described. A system includes a host and a memory device coupled to the host via an interconnect bus. The host includes a host security manager configured to encrypt data of a command, perform a memory integrity check, allow access to memory of a memory device corresponding to an address of a command based on which entity associated with the host sent the command, generate security keys, program security keys into the memory device, program encryption ranges, or any combination thereof. The memory device includes a memory encryption manager and a memory device security manager. The memory device security manager is configured to detect whether a command was sent from a trusted domain of the host or non-trusted domain of the host and identify which entity associated with the host initiated the command.

Abstract: Implementations described herein relate to dice failure correction using parity dice. In some implementations, a memory device may identify a plurality of dice that includes a set of data block dice and a set of parity dice. The memory device may detect one or more dice failures associated with the set of data block dice. The memory device may correct the one or more dice failures using the set of parity dice. The memory device may store corrected data associated with one or more corrected data block dice in one or more parity dice in the set of parity dice based on a reconfiguration of the set of parity dice. The memory device may apply remaining parity dice in the set of parity dice to correct one or more additional dice failures associated with the set of data block dice.

Abstract: A media management operation is initiated on a plurality of management units of one or more memory devices managed by the controller. A first error status and second error status associated with a read stage of the media management operation performed on a first management unit of the plurality of management units is received. An error correction operation on the first management unit is performed responsive to determining that the first error status and the second error status indicate a correctable error in the first management unit. An entry mapping a logical address to a physical address associated with the first management unit is locked responsive to determining that no spare management unit is available.

Abstract: Systems, methods, and apparatus for memory device security and row hammer mitigation are described. A control mechanism may be implemented in a front-end and/or a back-end of a memory sub-system to refresh rows of the memory. A row activation command having a row address at control circuitry of a memory sub-system and incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system may be received. Control circuitry may determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count may be incremented each time the CAM is full. A refresh command to the row address may be issued when a determination is made that the first count is greater than the RHT minus the second count.

Abstract: In some aspects, the techniques described herein relate to a device including: a datapath facilitating data transfers between a host device and a storage device; a firmware storage device storing a plurality of firmware tasks; and a processor, the processor including a hypervisor configured to: execute a given firmware task in the plurality of firmware tasks in a container, and control access to the datapath based on tags associated with instructions of the given firmware task.

Abstract: In some implementations, a memory system may receive, from a host system, an access request. The memory system may determine whether a valid bit structure, that is associated with the portion of the memory, is set to a first value or a second value, where the valid bit structure is set to the first value to indicate that a corresponding access counter is not valid or to the second value to indicate that a corresponding access counter is valid. The memory system may perform one of setting the valid bit structure to the second value and initializing an access counter that is associated with the valid bit structure based on determining that the valid bit structure is set to the first value, or incrementing the access counter based on determining that the valid bit structure is set to the second value.

Abstract: Implementations described herein relate to preventing profiled side channel attacks. A host device may obtain a first profiling configuration that is based on a plurality of keys and one or more characteristics of a first memory device and may obtain a second profiling configuration that is based on the plurality of keys and one or more characteristics of a second memory device. The host device may generate a model based on the first profiling configuration and the second profiling configuration. The host device may initiate or perform a profiled side channel attach using the model.

Abstract: Systems, apparatuses, and methods related to bloom filter implementation into a controller are described. A memory device is coupled to a memory controller. The memory controller is configured to implement a counting bloom filter, increment the counting bloom filter in response to a row activate command of the memory device, determine whether a value of the counting bloom filter exceeds a threshold value, and perform an action in response to the value exceeding the threshold value.

Abstract: Methods, systems, and devices related to firmware validation for firmware updates are disclosed. A controller can, in association with a firmware update of a memory module: determine whether first security information and first customer information of a manifest of a firmware package are valid using second security information and second customer information, respectively, stored by a non-volatile memory device of the memory module; determine whether a first public key of a first image of the firmware package is valid using a second public key of the manifest corresponding to the first image and associated with the first security information and the first customer information; and determine whether a third public key of a second image of the firmware package is valid using a fourth public key of the manifest corresponding to the second image and associated with the first security information and the first customer information.

Abstract: Methods, systems, and devices for log management maintenance operation and command are described. A method may include receiving, at a memory system, a command associated with maintenance for the memory system and indicating to initiate collecting values of a parameter, storing a value of the parameter, and transmitting, to a host system, a message indicating an availability of the value of the parameter based at least in part on storing the value of the parameter. An additional method may include transmitting, to a host system, a message indicating that a quantity of errors for an address of an address space associated with the memory system satisfies a threshold, receiving a command associated with maintenance for the memory system and indicating a retirement of the address, and retiring the address for the address space associated with the memory system based at least in part on receiving the command.

Abstract: An apparatus can include a number of memory devices and a memory controller coupled to one or more of the number of memory devices. The memory controller can include a row hammer detector. The memory controller can be configured increment for a first time period a row counter in a first data structure and a refresh counter. The memory controller can be configured to increment for a second time period a row counter in a second data structure and the refresh counter. The memory controller can be configured to determine that a value of the refresh counter exceeds a refresh threshold and responsive to the determination that the value of the refresh counter exceeds the refresh threshold, issue a notification.

Abstract: Provided in a central controller system, is a system and method to identify and mitigate errors on a die containing mission critical logical-to-physical addressing information. The logical-to-physical (L2P) addressing information is essential for translating logical memory addresses for uncompressed data to physical addresses for compressed data. When a die containing L2P data is detected as being corrupted, the corrupted data is corrected, and all the data is moved to an uncorrupted die at a specified offset from the original address of the die.

Abstract: A variety of applications can include a memory device having dynamic page mapping with compression. The memory device can include a mapping table having an entry location to associate a virtual page with a physical address of a first stripe of data of the virtual page. The entry location can include a flag along with the physical address of the first stripe. The flag can identify data of the virtual page as being compressed or uncompressed. A controller of the memory device, responsive to the flag identifying the data of virtual page being compressed, is structured to generate a format of compressed data of the first stripe with a header. The header can include a count of additional physical addresses to store compressed data of the virtual page and the additional physical addresses. Additional apparatus, systems, and methods are disclosed.

Abstract: Systems, apparatuses, and methods related to bloom filter implementation into a controller are described. A memory device is coupled to a memory controller. The memory controller is configured to implement a counting bloom filter, increment the counting bloom filter in response to a row activate command of the memory device, determine whether a value of the counting bloom filter exceeds a threshold value, and perform an action in response to the value exceeding the threshold value.

Abstract: In some implementations, a memory system controller may receive, from a host system, a memory-access request. The memory system controller may store an identifier associated with the memory-access request in a ring-buffer structure. The memory system controller may determine whether a data structure includes an entry associated with the identifier. The memory system controller may perform one of: updating a memory-access counter stored at the entry when the data structure does include the entry, or creating the entry in the data structure and initializing the memory-access counter stored at the entry when the data structure does not include the entry. The memory system controller may receive, from the host system, a request to read the data structure and/or may transmit, to the host system and based on the request, an indication of a respective identifier and a respective memory-access counter for each entry having a respective flag set.

Abstract: A method can include performing at least one glitch resistance operation and detecting, by a circuit included in a glitch detector coupled via a connection matrix to a first processing unit, an indication of a glitch on a memory system. The method can include notifying, via the connection matrix, at least a second processing unit of the detected indication of the glitch. The method can include subsequent to notifying at least the second processing unit, transmitting via the at least the second processing unit a glitch confirmation signal.