Abstract: A thermoelectric generator of compact size, having a simple structure configured for increasing the conversion efficiency of thermal energy into electric energy, so as it is possible to transform into electric current also as amount of heat per unit surface greater than thin film prior art devices, has a base silicon wafer and a cover silicon wafer, wherein the cover silicon wafer is facing said base silicon wafer in such a way that the respective top contacts are in contact and the space between the cover silicon wafer and the base silicon wafer is a space in which vacuum is made or a gas is present, in particular air.

Abstract: An integrated thermoelectric generator of out-of-plane heat flux configuration can be fabricated with a process fully compatible with standard front-end CMOS or BiCMOS technologies, if portions of the planar electrically non conductive cover layer suspended over the valleys have sufficiently large through holes to let isotropic etching solutions or etching plasma pass therethrough, across the thickness of the non conductive cover layer, so as to realize void spaces. The generator has a top capping layer deposited onto a free surface, oriented in an opposite direction in respect to the void spaces, of the planar electrically non conductive cover layer so as to occlude the through holes of the non conductive cover layer. A method of fabricating an integrated thermoelectric generator of out-of-plane heat flux configuration is also disclosed.

Abstract: A thermoelectric generator of compact size, having a simple structure configured for increasing the conversion efficiency of thermal energy into electric energy, so as it is possible to transform into electric current also as amount of heat per unit surface greater than thin film prior art devices, has a base silicon wafer and a cover silicon wafer, wherein the cover silicon wafer is facing said base silicon wafer in such a way that the respective top contacts are in contact and the space between the cover silicon wafer and the base silicon wafer is a space in which vacuum is made or a gas is present, in particular air.

Abstract: An enhanced electrical yield is achieved with an integrated thermoelectric generator (iTEG) of out-of-plane heat flux configuration on a substrate wafer having hill-top junction metal contacts and valley-bottom junction metal contacts joining juxtaposed ends of segments, alternately p-doped and n-doped, of defined thin film lines of segments of a polycrystalline semiconductor, extending over inclined opposite flanks of hills of a material of lower thermal conductivity than the thermal conductivity of the thermoelectrically active polycrystalline semiconductor, by keeping void the valleys spaces (V) among the hills and delimited at the top by a planar electrically non conductive cover with metal bond pads defined over the coupling surface, adapted to bond with respective hill-top junction metal contacts. The junction metal contacts have a cross sectional profile of low aspect ratio, with two arms or wings overlapping the juxtaposed end portions of the segments.

Abstract: Disclosed are two geometrically identical integrated Z-device structures, integrated in two distinct silicon dices, joined together in a face-to-face configuration, such that a p-doped thin film leg of one structure faces toward a n-doped thin film leg of the other structure and vice versa. Upon joining the Z-device structures together, the hill-top metal contacts of one integrated structure are bonded in electrical and thermal continuity with correspondent hill-top metal contacts of the other integrated structure, forming a substantially bivalve TEG of increased power yield for the same footprint area and having an enhanced conversion efficiency. Thermo-electrically generated current may be gathered from one or several end pad pairs, the pads of which are connected to respective valley bottom contacts, on one and on the other of the two dices of the bivalve device, at the ends of conductive lines of micro cells respectively belonging to one and to the other of the two coupled dices.

Abstract: Dices of integrated Z-device structures on a substrate wafer of a 3D integrated thermo-electric generator (iTEG) may be stacked in a tri-dimensional heterogeneous integration mode, without or with interposer wafer dices, in coherent thermal coupling among them. Through silicon vias (TSVs) holes through the thickness of the semiconductor crystal of substrate of the dices of integrated Z-device structures in geometrical projection correspondence with valley bottom metal junction contacts, and through silicon vias (TSVs) holes through the thickness of the semiconductor crystal of interposer dices, in geometrical projection correspondence with the hill-top metal junction contacts of the coupled Z-device structures, have a copper or other good heat conductor filler, form low thermal resistance heat conduction paths through the stacked Z-device structures. Thermoelectrically generated current is gathered from every integrated Z-device of a multi-tier iTEG operating in an out-of-plane heat flux configuration.

Abstract: Dices of integrated Z-device structures on a substrate wafer of a 3D integrated thermo-electric generator (iTEG) may be stacked in a tri-dimensional heterogeneous integration mode, without or with interposer wafer dices, in coherent thermal coupling among them. Through silicon vias (TSVs) holes through the thickness of the semiconductor crystal of substrate of the dices of integrated Z-device structures in geometrical projection correspondence with valley bottom metal junction contacts, and through silicon vias (TSVs) holes through the thickness of the semiconductor crystal of interposer dices, in geometrical projection correspondence with the hill-top metal junction contacts of the coupled Z-device structures, have a copper or other good heat conductor filler, form low thermal resistance heat conduction paths through the stacked Z-device structures. Thermoelectrically generated current is gathered from every integrated Z-device of a multi-tier iTEG operating in an out-of-plane heat flux configuration.

Abstract: Disclosed are two geometrically identical integrated Z-device structures, integrated in two distinct silicon dices, joined together in a face-to-face configuration, such that a p-doped thin film leg of one structure faces toward a n-doped thin film leg of the other structure and vice versa. Upon joining the Z-device structures together, the hill-top metal contacts of one integrated structure are bonded in electrical and thermal continuity with correspondent hill-top metal contacts of the other integrated structure, forming a substantially bivalve TEG of increased power yield for the same footprint area and having an enhanced conversion efficiency. Thermo-electrically generated current may be gathered from one or several end pad pairs, the pads of which are connected to respective valley bottom contacts, on one and on the other of the two dices of the bivalve device, at the ends of conductive lines of micro cells respectively belonging to one and to the other of the two coupled dices.

Abstract: An enhanced electrical yield is achieved with an integrated thermoelectric generator (iTEG) of out-of-plane heat flux configuration on a substrate wafer having hill-top junction metal contacts and valley-bottom junction metal contacts joining juxtaposed ends of segments, alternately p-doped and n-doped, of defined thin film lines of segments of a polycrystalline semiconductor, extending over inclined opposite flanks of hills of a material of lower thermal conductivity than the thermal conductivity of the thermoelectrically active polycrystalline semiconductor, by keeping void the valleys spaces (V) among the hills and delimited at the top by a planar electrically non conductive cover with metal bond pads defined over the coupling surface, adapted to bond with respective hill-top junction metal contacts. The junction metal contacts have a cross sectional profile of low aspect ratio, with two arms or wings overlapping the juxtaposed end portions of the segments.

Abstract: A method for realizing a nanometric circuit architecture includes: realizing plural active areas on a semiconductor substrate; realizing on the substrate a seed layer of a first material; realizing a mask-spacer of a second material on the seed layer in a region comprised between the active areas; realizing a mask overlapping the mask-spacer and extending in a substantially perpendicular direction thereto; selectively removing the seed layer exposed on the substrate; selectively removing the mask and the mask-spacer obtaining a seed-spacer comprising a linear portion extending in that region and a portion substantially orthogonal thereto; realizing by MSPT from the seed-spacer an insulating spacer reproducing at least part of the profile of the seed-spacer; realizing by MSPT a nano-wire of conductive material from the seed-spacer or insulating spacer, the nano-wire comprising a first portion at least partially extending in the region and a second portion contacting a respective active area.

Abstract: Nanosized filamentary carbon structures (CNTs) nucleating over a catalyzed surface may be grown in an up-right direction reaching a second surface, spaced from the first surface, without the need of applying any external voltage source bias. The growth process may be inherently self-stopping, upon reaching a significant population of grown CNTs on the second surface. A gap between the two surfaces may be defined for CNT devices being simultaneously fabricated by common integrated circuit integration techniques. The process includes finding that for separation gaps of up to a hundred or more nanometers, a difference between the respective work functions of the materials delimiting the gap space, for example, different metallic materials or a doped semiconductor of different dopant concentration or type, may produce an electric field intensity orienting the growth of nucleated CNTs from the surface of one of the materials toward the surface of the other material.

Abstract: Nanosized filamentary carbon structures (CNTs) nucleating over a catalyzed surface may be grown in an up-right direction reaching a second surface, spaced from the first surface, without the need of applying any external voltage source bias. The growth process may be inherently self-stopping, upon reaching a significant population of grown CNTs on the second surface. A gap between the two surfaces may be defined for CNT devices being simultaneously fabricated by common integrated circuit integration techniques. The process includes finding that for separation gaps of up to a hundred or more nanometers, a difference between the respective work functions of the materials delimiting the gap space, for example, different metallic materials or a doped semiconductor of different dopant concentration or type, may produce an electric field intensity orienting the growth of nucleated CNTs from the surface of one of the materials toward the surface of the other material.

Abstract: Nanosized filamentary carbon structures (CNTs) nucleating over a catalyzed surface may be grown in an up-right direction reaching a second surface, spaced from the first surface, without the need of applying any external voltage source bias. The growth process may be inherently self-stopping, upon reaching a significant population of grown CNTs on the second surface. A gap between the two surfaces may be defined for CNT devices being simultaneously fabricated by common integrated circuit integration techniques. The process includes finding that for separation gaps of up to a hundred or more nanometers, a difference between the respective work functions of the materials delimiting the gap space, for example, different metallic materials or a doped semiconductor of different dopant concentration or type, may produce an electric field intensity orienting the growth of nucleated CNTs from the surface of one of the materials toward the surface of the other material.

Abstract: A nanometric device comprising a substrate; a plurality of conductive spacers of a conductive material, each conductive spacer being arranged on top of and transverse to the substrate, the conductive spacers including respective pairs of conductive spacers defining respective hosting seats each of less than 30 nm wide; and a plurality of nanometric elements respectively accommodated in the hosting seats.

Abstract: A method for realizes electric connections in a semiconductor electronic device between a nanometric circuit architecture and standard electronic components.

Abstract: A semiconductor electronic device that includes a semiconductor substrate having a top surface; a seed layer positioned on the substrate and having a notched wall extending transversely with respect to the substrate top surface, the wall defining a first recess extending into the seed layer with a height equal to a thickness of the seed layer; a first conductive nanowire in contact with the notched wall, the first conductive nanowire having a contact portion extending into the first recess and covering opposite sidewalls and a bottom of the first recess; a first insulating nanowire in contact with a sidewall of the first conductive nanowire; an insulating layer on the contact portion of the first conductive nanowire and having a first window substantially in correspondence with the contact portion of the first conductive nanowire; and a first conductive die on the insulating layer that includes a conductive contact extending into the first window and contacting the contact portion of the first conductive nano

Abstract: A method realizes a multispacer structure including an array of spacers having same height. The method includes realizing, on a substrate, a sacrificial layer of a first material; b) realizing, on the sacrificial layer, a sequence of mask spacers obtained by SnPT, which are alternately obtained in at least two different materials; c) chemically etching one of the two different materials with selective removal of the mask spacers of this etched material and partial exposure of the sacrificial layer; d) chemically and/or anisotropically etching the first material with selective removal of the exposed portions of the sacrificial layer; e) chemically etching the other one of the two different materials with selective removal of the mask spacers of this etched material and obtainment of the multispacer structure.

Abstract: A hosting structure of nanometric components is described advantageously comprising: a substrate; n array levels on said substrate, with n?2, arranged consecutively on growing and parallel planes, each including a plurality of conductive spacers alternated with a plurality of insulating spacers and substantially perpendicular to said substrate, with definition between consecutive conductive spacers of at least a gap, conductive spacers of consecutive array levels lying on distinct and parallel planes, said gaps of different array levels being at least partially aligned along a direction substantially perpendicular to said substrate with definition of a plurality of transversal hosting seats extended along said direction and suitable for hosting at least a nanometric component. A nanometric electronic device is also described comprising such a hosting structure and a method for realizing it.

Abstract: Nanosized filamentary carbon structures (CNTs) nucleating over a catalyzed surface may be grown in an up-right direction reaching a second surface, spaced from the first surface, without the need of applying any external voltage source bias. The growth process may be inherently self-stopping, upon reaching a significant population of grown CNTs on the second surface. A gap between the two surfaces may be defined for CNT devices being simultaneously fabricated by common integrated circuit integration techniques. The process includes finding that for separation gaps of up to a hundred or more nanometers, a difference between the respective work functions of the materials delimiting the gap space, for example, different metallic materials or a doped semiconductor of different dopant concentration or type, may produce an electric field intensity orienting the growth of nucleated CNTs from the surface of one of the materials toward the surface of the other material.

Abstract: A method and device demultiplex a crossbar non-volatile memory that includes a first array of row nano-wires and a second array of column nano-wires, which cross the row nano-wires at a plurality of cross-points, hosting plural memory cells. A first electrode and a second electrode respectively cross a modulated doping portion of the row nano-wires and a modulated doping portion of the column nano-wires. A first contact and a second contact respectively the row nano-wires and the column nano-wires. The first electrode and the second electrode are biased respectively with a first and a second adjustable voltage value that progressively switch one by one said memory cells from the OFF state to the ON state, and this state can be memorized.