Patents by Inventor Danilo Rimondi
Danilo Rimondi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9263120Abstract: An embodiment of a memory device of SRAM type is proposed. The memory device includes a plurality of memory cells each for storing a first logic value represented by a first reference voltage or a second logic value represented by a second reference voltage. Each memory cell includes a bistable latch—having a main terminal, a complementary terminal, a set of main storage transistors for maintaining the main terminal at the reference voltage corresponding to the stored logic value, and a set of complementary storage transistors to maintain the complementary terminal at the reference voltage corresponding to the complement of the stored logic value—a main access transistor and a complementary access transistor for accessing the main terminal and the complementary terminal, respectively.Type: GrantFiled: June 30, 2011Date of Patent: February 16, 2016Assignee: STMicroelectronics S.r.l.Inventors: Danilo Rimondi, Carolina Selva
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Patent number: 9245606Abstract: A static random access memory (SRAM) device includes a memory array of a plurality of memory cells, a controller that receives an external clock signal formed by a succession of external pulses and generates an internal clock signal formed by a succession of internal pulses, and a driving circuit that receives the internal clock signal. The controller is operable in a first mode, wherein the controller generates, for each external pulse, a corresponding internal pulse and the controller controls the driving circuit so that the driving circuitry carries out one access to the memory array for each internal pulse. The controller is further operable in a second mode, wherein the controller generates, for each external pulse, a pair of internal pulses, and the controller controls the driving circuitry so that, for each pair of internal pulses, the driving circuitry writes a first data item in a set of memory cells, and then reads the set of memory cells, so as to acquire a second data item.Type: GrantFiled: November 20, 2012Date of Patent: January 26, 2016Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS S.R.L.Inventors: Danilo Rimondi, Carolina Selva, Ashish Kumar
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Patent number: 8588018Abstract: A method for testing a memory device. The memory device includes a matrix of memory cells having a plurality of rows and columns; the matrix includes a plurality of rows of operative memory cells each one for storing a variable value and at least one row of auxiliary memory cells each one storing a fixed value. The memory device further includes writing circuitry for writing selected values into the operative memory cells, and reading circuitry for reading the values being stored from the operative or auxiliary memory cells. The method includes reading output values from the row of auxiliary memory cells, determining a malfunctioning of the memory device in response to a missing match of the output values with the fixed values, determining a cause of the malfunctioning according to a pattern of reading errors between the output values and the corresponding fixed values, and providing a signal indicative of the cause of the malfunctioning.Type: GrantFiled: November 26, 2012Date of Patent: November 19, 2013Assignee: STMicroelectronics S.r.l.Inventors: Danilo Rimondi, Carolina Selva
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Patent number: 8537602Abstract: An embodiment of a memory device of SRAM type integrated in a chip of semiconductor material is proposed. The memory device includes a plurality of memory cells each for storing a binary data having a first logic value represented by a first reference voltage or a second logic value represented by a second reference voltage. Each memory cell includes a bistable latch—having a main terminal, a complementary terminal, a set of field effect main storage transistors coupled to the main terminal for maintaining the main terminal at the reference voltage corresponding to the stored logic value or to a complement thereof, a set of field effect complementary storage transistors coupled to the complementary terminal for maintaining the complementary terminal at the reference voltage corresponding to the complement of the logic value associated with the main terminal—and a field effect access transistor for accessing the main terminal.Type: GrantFiled: June 30, 2011Date of Patent: September 17, 2013Assignee: STMicroelectronics S.r.l.Inventors: Danilo Rimondi, Carolina Selva
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Patent number: 8400820Abstract: An embodiment of a memory device includes a plurality of memory cells; each memory cell includes a latch adapted to store an information bit. Said latch includes a first logic gate including a first input terminal and a first output terminal and a second logic gate including a second input terminal and a second output terminal. Said first input terminal is connected to said second output terminal and said first output terminal is connected to said second input terminal. The memory device further includes reading and writing means adapted to perform a read operation or a write operation of the information bit. Said first logic gate includes a pull-up branch coupled between a terminal for providing a supply voltage and the first output terminal, and a pull-down branch coupled between the first output terminal and a terminal for providing a reference voltage.Type: GrantFiled: December 21, 2010Date of Patent: March 19, 2013Assignee: STMicroelectronics S.r.l.Inventors: Danilo Rimondi, Donatella Brambilla, Rita Zappa, Carolina Selva
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Patent number: 8320207Abstract: A method for testing a memory device. The memory device includes a matrix of memory cells having a plurality of rows and columns; the matrix includes a plurality of rows of operative memory cells each one for storing a variable value and at least one row of auxiliary memory cells each one storing a fixed value. The memory device further includes writing circuitry for writing selected values into the operative memory cells, and reading circuitry for reading the values being stored from the operative or auxiliary memory cells. The method includes reading output values from the row of auxiliary memory cells, determining a malfunctioning of the memory device in response to a missing match of the output values with the fixed values, determining a cause of the malfunctioning according to a pattern of reading errors between the output values and the corresponding fixed values, and providing a signal indicative of the cause of the malfunctioning.Type: GrantFiled: December 3, 2010Date of Patent: November 27, 2012Assignee: STMicroelectronics S.r.l.Inventors: Danilo Rimondi, Carolina Selva
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Patent number: 8161327Abstract: A method is for making an integrated circuit with built-in self-test. The method includes forming at least one nonvolatile read only memory (ROM) to store ROM code and forming a logic self-test circuit to verify a correct functioning of the at least one nonvolatile ROM. Moreover, the method includes defining, in the logic self-test circuit, a logic self-test core to process the ROM code and to generate a flag based upon a control signature and defining, in the logic self-test circuit, a nonvolatile storage block, coupled to the logic self-test core, to store the control signature. Furthermore, the method includes writing the ROM code to the at least one nonvolatile ROM and writing the control signature to the nonvolatile storage block, during a same fabrication step.Type: GrantFiled: April 11, 2008Date of Patent: April 17, 2012Assignee: STMicroelectronics S.R.L.Inventors: Carolina Selva, Cosimo Torelli, Danilo Rimondi, Rita Zappa
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Publication number: 20120002459Abstract: An embodiment of a memory device of SRAM type integrated in a chip of semiconductor material is proposed. The memory device includes a plurality of memory cells each for storing a binary data having a first logic value represented by a first reference voltage or a second logic value represented by a second reference voltage. Each memory cell includes a bistable latch—having a main terminal, a complementary terminal, a set of field effect main storage transistors coupled to the main terminal for maintaining the main terminal at the reference voltage corresponding to the stored logic value or to a complement thereof, a set of field effect complementary storage transistors coupled to the complementary terminal for maintaining the complementary terminal at the reference voltage corresponding to the complement of the logic value associated with the main terminal—and a field effect access transistor for accessing the main terminal.Type: ApplicationFiled: June 30, 2011Publication date: January 5, 2012Applicant: STMICROELECTRONICS S.R.L.Inventors: Danilo RIMONDI, Carolina SELVA
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Publication number: 20120002460Abstract: An embodiment of a memory device of SRAM type is proposed. The memory device includes a plurality of memory cells each for storing a first logic value represented by a first reference voltage or a second logic value represented by a second reference voltage. Each memory cell includes a bistable latch—having a main terminal, a complementary terminal, a set of main storage transistors for maintaining the main terminal at the reference voltage corresponding to the stored logic value, and a set of complementary storage transistors to maintain the complementary terminal at the reference voltage corresponding to the complement of the stored logic value—a main access transistor and a complementary access transistor for accessing the main terminal and the complementary terminal, respectively.Type: ApplicationFiled: June 30, 2011Publication date: January 5, 2012Applicant: STMICROELECTRONICS S.R.L.Inventors: Danilo RIMONDI, Carolina SELVA
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Publication number: 20110157954Abstract: An embodiment of a memory device includes a plurality of memory cells; each memory cell includes a latch adapted to store an information bit. Said latch includes a first logic gate including a first input terminal and a first output terminal and a second logic gate including a second input terminal and a second output terminal. Said first input terminal is connected to said second output terminal and said first output terminal is connected to said second input terminal. The memory device further includes reading and writing means adapted to perform a read operation or a write operation of the information bit. Said first logic gate includes a pull-up branch coupled between a terminal for providing a supply voltage and the first output terminal, and a pull-down branch coupled between the first output terminal and a terminal for providing a reference voltage.Type: ApplicationFiled: December 21, 2010Publication date: June 30, 2011Applicant: STMICROELECTRONICS S.R.L.Inventors: Danilo RIMONDI, Donatella BRAMBILLA, Rita ZAPPA, Carolina SELVA
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Publication number: 20110158016Abstract: A method for testing a memory device. The memory device includes a matrix of memory cells having a plurality of rows and columns; the matrix includes a plurality of rows of operative memory cells each one for storing a variable value and at least one row of auxiliary memory cells each one storing a fixed value. The memory device further includes writing circuitry for writing selected values into the operative memory cells, and reading circuitry for reading the values being stored from the operative or auxiliary memory cells. The method includes reading output values from the row of auxiliary memory cells, determining a malfunctioning of the memory device in response to a missing match of the output values with the fixed values, determining a cause of the malfunctioning according to a pattern of reading errors between the output values and the corresponding fixed values, and providing a signal indicative of the cause of the malfunctioning.Type: ApplicationFiled: December 3, 2010Publication date: June 30, 2011Applicant: STMicroelectronics S.r.I.Inventors: Danilo Rimondi, Carolina Selva
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Patent number: 7571367Abstract: A self diagnosis (BISD) device for a random memory array, preferably integrated with the random access memory, executes a certain number of predefined test algorithms and identifies addresses of faulty locations. The BISD device recognizes certain fail patterns of interest and generates bit-strings corresponding to them. In practice, the BISD device may diagnose memory arrays and allow the identification of defects in the production process that affect a new technology during its learning phase, thus accelerating its maturation.Type: GrantFiled: August 5, 2005Date of Patent: August 4, 2009Assignee: STMicroelectronics S.r.l.Inventors: Carolina Selva, Rita Zappa, Danilo Rimondi, Cosimo Torelli, Giovanni Mastrodomenico
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Publication number: 20080256407Abstract: A method is for making an integrated circuit with built-in self-test. The method includes forming at least one nonvolatile read only memory (ROM) to store ROM code and forming a logic self-test circuit to verify a correct functioning of the at least one nonvolatile ROM. Moreover, the method includes defining, in the logic self-test circuit, a logic self-test core to process the ROM code and to generate a flag based upon a control signature and defining, in the logic self-test circuit, a nonvolatile storage block, coupled to the logic self-test core, to store the control signature. Furthermore, the method includes writing the ROM code to the at least one nonvolatile ROM and writing the control signature to the nonvolatile storage block, during a same fabrication step.Type: ApplicationFiled: April 11, 2008Publication date: October 16, 2008Applicant: STMicroelectronics S.r.l.Inventors: Carolina Selva, Cosimo Torelli, Danilo Rimondi, Rita Zappa
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Publication number: 20080151675Abstract: An integrated circuit includes an array of memory cells arranged in a plurality of sectors. Each sector includes a plurality of distinct random access memory resources able to be accessed differently in different modes. Peripheral circuitry is commonly shared by at least some of the sectors for addressing and reading/writing data. A respective dedicated controllable power supply line is coupled to each sector.Type: ApplicationFiled: December 21, 2007Publication date: June 26, 2008Applicant: STMicroelectronics S.r.I.Inventors: Cosimo Torelli, Danilo Rimondi, Rita Zappa
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Patent number: 7284166Abstract: A built-in self-test and self-repair structure (BISR) of memory arrays embedded in an integrated device includes at least a test block (BIST) programmable to execute on a respective memory array of the device any of a certain number of test algorithms, and a self-repair block that includes a column address generator processing the faulty address information for allocating redundant resources of the tested memory array. The BISR may further include a redundancy register on which final redundancy information is loaded at each power-on of the device and control logic for managing data transfer from external circuitry to the built-in self-test and self-repair structure (BISR) and vice versa. The BIST structure serves any number of embedded memory arrays even of different types and sizes.Type: GrantFiled: August 5, 2005Date of Patent: October 16, 2007Assignee: STMicroelectronics S.r.l.Inventors: Rita Zappa, Carolina Selva, Danilo Rimondi, Cosimo Torelli
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Publication number: 20060031726Abstract: A built-in self-test and self-repair structure (BISR) of memory arrays embedded in an integrated device includes at least a test block (BIST) programmable to execute on a respective memory array of the device any of a certain number of test algorithms, and a self-repair block that includes a column address generator processing the faulty address information for allocating redundant resources of the tested memory array. The BISR may further include a redundancy register on which final redundancy information is loaded at each power-on of the device and control logic for managing data transfer from external circuitry to the built-in self-test and self-repair structure (BISR) and vice versa. The BIST structure serves any number of embedded memory arrays even of different types and sizes.Type: ApplicationFiled: August 5, 2005Publication date: February 9, 2006Applicant: STMicroelectronics S.r.l.Inventors: Rita Zappa, Carolina Selva, Danilo Rimondi, Cosimo Torelli
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Publication number: 20060028891Abstract: A self diagnosis (BISD) device for a random memory array, preferably integrated with the random access memory, executes a certain number of predefined test algorithms and identifies addresses of faulty locations. The BISD device recognizes certain fail patterns of interest and generates bit-strings corresponding to them. In practice, the BISD device may diagnose memory arrays and allow the identification of defects in the production process that affect a new technology during its learning phase, thus accelerating its maturation.Type: ApplicationFiled: August 5, 2005Publication date: February 9, 2006Applicant: STMicroelectronics S.r.I.Inventors: Carolina Selva, Rita Zappa, Danilo Rimondi, Cosimo Torelli, Giovanni Mastrodomenico
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Patent number: 6963499Abstract: A memory cell comprises a first and a second inverters connected in a latch configuration. The inverters have respective first and second means for receiving a first and a second voltage supplies, respectively. The cell also comprises means, responsive to a memory cell selection signal, for selectively connecting an input of at least one of the first and second inverter to at least one respective input/output data line, carrying an input datum to be written in the memory cell in a memory cell write operation and an output datum read from the memory cell in a memory cell read operation. For flash-clearing the memory cell, means are provided for switching at least one of the first and second voltage supply receiving means of at least one of the first and second inverters between the first voltage supply and the second voltage supply. The memory cell is particularly adapted to implement a flash-clear function in a memory device.Type: GrantFiled: December 27, 2002Date of Patent: November 8, 2005Assignee: STMicroelectronics S.r.l.Inventors: Danilo Rimondi, Cosimo Torelli
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Publication number: 20030231538Abstract: A memory cell comprises a first and a second inverters connected in a latch configuration. The inverters have respective first and second means for receiving a first and a second voltage supplies, respectively. The cell also comprises means, responsive to a memory cell selection signal, for selectively connecting an input of at least one of the first and second inverter to at least one respective input/output data line, carrying an input datum to be written in the memory cell in a memory cell write operation and an output datum read from the memory cell in a memory cell read operation. For-flash-clearing the memory cell, means are provided for switching at least one of the first and second voltage supply receiving means of at least one of the first and second inverters between the first voltage supply and the second voltage supply. The memory cell is particularly adapted to implement a flash-clear function in a memory device.Type: ApplicationFiled: December 27, 2002Publication date: December 18, 2003Applicant: STMicroelectronics S.r.I.Inventors: Danilo Rimondi, Cosimo Torelli
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Publication number: 20030026150Abstract: A semiconductor memory cell having a word line, a bit line, a precharge line, an access transistor, and first and second cross-coupled inverters. The first inverter includes a first P-channel transistor and a first N-channel transistor, and the second inverter includes a second P-channel transistor and a second N-channel transistor. The access transistor selectively couples the bit line to an output of the first or second inverter, and one terminal of the first N-channel transistor is connected to the precharge line. In a preferred embodiment, a control circuit is provided that, during a writing operation, supplies data to be written to the memory cell to the bit line, supplies a pulse signal to the precharge line, and activates the word line. A method of writing data to a semiconductor memory cell that is coupled to a word line and single bit line is also provided.Type: ApplicationFiled: September 24, 2002Publication date: February 6, 2003Applicant: STMicroelectronics S.r.I.Inventor: Danilo Rimondi