Abstract: A self test structure for interconnect and logic element testing in programmable devices including a plurality of logic elements; an interconnect structure for connecting the logic elements; SRAM based configuration latches for configuring the interconnect structure; test configuration circuitry for configuring any desired set of logic elements, interconnect structure and configuration latches during reset state that links the logic elements and interconnect structure to form a complete path between the interface points of the programmable logic device to enable testing of the desired elements in the complete path.

Abstract: An efficient Content Addressable Memory array for Classless Inter-Domain Routing with each CAM cell including an additional storage unit for storing the prefix length associated with the contents of the cell. An enabling logic connects the prefix length value to a wired OR plane common to all CAM cells, and a sequential bit wise comparison unit has its inputs connected to the wired OR plane and the additional storage unit with its output controlling the enabling logic.

Abstract: A Content Addressable Memory (CAM) with an improved the priority encoder enabling random storage of CIDR IP addresses in memory, including a plurality of data storage elements each having a first compare circuit for comparing a search key with the content of the data storage elements, the data storage elements storing data and associated prefix lengths; a match line associated with each first compare circuit to receive a signal representing a match or a mismatch of the compare data; and a priority encoder that receives match line signals and prefix lengths from data storage elements and provides a memory location address that corresponds to the matched longest prefix.

Abstract: An improved Built-In-Self-Test (BIST) architecture for Content Addressable Memory (CAM) devices, comprising a bit scanner for reading out the contents of the matchlines of the CAM cells as a serial bit stream; a bit transition detector that detects and determines the address of each bit transition in the serial bit stream; a state machine that generates bit addresses for each expected transition in the serial bit stream; and an analyser that compares expected transition bit addresses with detected transition addresses and declares a BIST failure if expected and detected transition addresses do not match at any point in the bit stream.