Patents by Inventor DANKA GOLDIN SCHWABOVA

DANKA GOLDIN SCHWABOVA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Stacked semiconductor package having fault detection and a method for identifying a fault in a stacked package
    Patent number: 9972611
    Abstract: A stacked semiconductor package comprising a functional silicon die having embedded thereupon a Wide Input/Output 2 (WIO2) interface, and two or more memory dies forming a corresponding two or more memory layers of the stacked semiconductor package. A plurality of Through Silicon Vias (TSVs) are formed through the two or more memory dies, wherein each of the plurality of TSVs traverse through the two or more memory layers to the functional silicon die via the WIO2 interface of the functional silicon die. A test port interface receives test signals from an external tester and routes the test signals through a steering logic communicably interfaced with the two or more memory dies. The steering logic shifts data into and out of the two or more memory dies through the plurality of TSVs.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: May 15, 2018
    Assignee: Intel Corporation
    Inventors: Lakshminarayana Pappu, Baruch Schnarch, Christopher J. Nelson, Danka Goldin Schwabova
  • A STACKED SEMICONDUCTOR PACKAGE HAVING FAULT DETECTION AND A METHOD FOR IDENTIFYING A FAULT IN A STACKED PACKAGE
    Publication number: 20180096979
    Abstract: A stacked semiconductor package comprising a functional silicon die having embedded thereupon a Wide Input/Output 2 (WIO2) interface, and two or more memory dies forming a corresponding two or more memory layers of the stacked semiconductor package. A plurality of Through Silicon Vias (TSVs) are formed through the two or more memory dies, wherein each of the plurality of TSVs traverse through the two or more memory layers to the functional silicon die via the WIO2 interface of the functional silicon die. A test port interface receives test signals from an external tester and routes the test signals through a steering logic communicably interfaced with the two or more memory dies. The steering logic shifts data into and out of the two or more memory dies through the plurality of TSVs.
    Type: Application
    Filed: March 31, 2017
    Publication date: April 5, 2018
    Inventors: LAKSHMINARAYANA PAPPU, BARUCH SCHNARCH, CHRISTOPHER J. NELSON, DANKA GOLDIN SCHWABOVA