Abstract: Hybrid multi-level memory architecture technologies are described. A System on Chip (SOC) includes multiple functional units and a multi-level memory controller (MLMC) coupled to the functional units. The MLMC is coupled to a hybrid multi-level memory architecture including a first-level dynamic random access memory (DRAM) (near memory) that is located on-package of the SOC and a second-level DRAM (far memory) that is located off-package of the SOC. The MLMC presents the first-level DRAM and the second-level DRAM as a contiguous addressable memory space and provides the first-level DRAM to software as additional memory capacity to a memory capacity of the second-level DRAM. The first-level DRAM does not store a copy of contents of the second-level DRAM.

Abstract: Hybrid multi-level memory architecture technologies are described. A System on Chip (SOC) includes multiple functional units and a multi-level memory controller (MLMC) coupled to the functional units. The MLMC is coupled to a hybrid multi-level memory architecture including a first-level dynamic random access memory (DRAM) (near memory) that is located on-package of the SOC and a second-level DRAM (far memory) that is located off-package of the SOC. The MLMC presents the first-level DRAM and the second-level DRAM as a contiguous addressable memory space and provides the first-level DRAM to software as additional memory capacity to a memory capacity of the second-level DRAM. The first-level DRAM does not store a copy of contents of the second-level DRAM.

Abstract: Memory bandwidth management. In a two-level memory (2LM) system far memory bandwidth utilization at least a far memory is monitored and the available far memory bandwidth availability is dynamically modified based on monitored far memory bandwidth utilization. The operational state of at least one processing core is dynamically modified in response to modification of available far memory bandwidth.

Abstract: Memory bandwidth management. In a two-level memory (2LM) system far memory bandwidth utilization at least a far memory is monitored and the available far memory bandwidth availability is dynamically modified based on monitored far memory bandwidth utilization. The operational state of at least one processing core is dynamically modified in response to modification of available far memory bandwidth.

Abstract: Unitary transceiving units employ a multiple carrier, time-division-multiple-access (TDMA), time-division-duplex (TDD protocol to conduct concurrent wireless voice and data communications wherein a first transceiving base station unit tethered to a network interface wirelessly communicates to a second, mobile transceiving unit. The mobile transceiving unit wirelessly transmits and receives packetized voice and data information that is separated and routed to respective voice or data networks. The unitary mobile transceiving unit thus functions as a concurrent voice phone and data communications terminal/computer.

Abstract: Unitary transceiving units employ a multiple carrier, time-division-multiple-access (TDMA), time-division-duplex (TDD protocol to conduct concurrent wireless voice and data communications wherein a first transceiving base station unit tethered to a network interface wirelessly communicates to a second, mobile transceiving unit. The mobile transceiving unit wirelessly transmits and receives packetized voice and data information that is separated and routed to respective voice or data networks. The unitary mobile transceiving unit thus functions as a concurrent voice phone and data communications terminal/computer.

Abstract: A system and method employs standard DECT hardware adapted for use in the Industrial-Scientific-Medical (ISM) Spectrum wherein a Frequency Hopping Spread Spectrum (FHSS), multiple carrier, time-division-multiple-access (TDMA), time-division-duplex (TDD) technique provides wireless communications over the ISM Spectrum while employing standard DECT hardware. A baseband processor provides slot and frame timing to a RF sub-module wherein the preferred, although not exclusive number of carrier frequencies is programmed to seventy-five ranging between 2401.122 MHz to 2479.813 MHz and spaced 1.063 MHz apart and wherein each of the seventy-five channels supports a ten-millisecond frame preferably, although not exclusively, comprised of sixteen time slots.