Abstract: A method is provided for configuring a programmable semiconductor device. The method includes using the configuration data of a macro (53A) or a plurality of macros to configure the programmable semiconductor device. The configuration data of the macro (53A) is combined with the configuration data of a work area (10). The programmable semiconductor device is configured using the combined configuration data of the macro (53A) and the work area (10).

Abstract: A system for laying out a capacitor array (400) implements a programmable capacitor (33-39) whose operation is controlled with a binary control word. A programmable capacitance is produced by coupling binary weighted, switchable capacitors (101-107) between terminals (51, 52) of the programmable capacitor. The capacitor array includes two or more unit capacitors (101, 103) of unequal areas. The other capacitors in the array are derived by interconnecting multiple capacitors that match one of the unit capacitors. Die area is reduced while accuracy is maintained by controlling the larger unit capacitor with the least significant bit of the binary control word whenever possible and using the smaller unit capacitor only as a trim capacitor.

Abstract: A clock circuit for generating alternate clock phases (P.sub.1, P.sub.2) whose trailing edges define sampling points of an analog-to-digital converter (106). Complementary signals (CLOCK0, CLOCK1) are generated from a system clock (F.sub.SYS) and switched through transmission gates (340-341, 342-343) when an enable signal (V.sub.EN) is applied. The system clock (F.sub.SYS) is delayed by a delay circuit (316) to produce the enable signal (V.sub.EN) after the complementary signals (CLOCK0, CLOCK1) are stable, thereby synchronizing the complementary signals (CLOCK0, CLOCK1) with the enable signal (V.sub.EN).

Abstract: A programmable analog array (10) comprises an array of configurable cells (11), each cell (11) including analog circuitry (12) and digital circuitry (14). The cells (11) are configured for a particular functional application. The digital circuitry (14) converts an analog signal generated by the analog circuitry (12) into digital control information, which is then used to adjust the analog circuitry (12). Therefore, the analog circuitry (12) and the digital circuitry (14) form a digital feedback loop. The digital feedback loop is established either within a single cell or among neighboring cells. Thus, the digital feedback loop is established without using a global data bus.

Abstract: A programmable capacitor array (10, 10') and a method for programming the programmable capacitor array (10, 10'). The programmable capacitor array (10, 10') includes an array of capacitors (C.sub.0 -C.sub.n), wherein each capacitor of the array of capacitors (C.sub.0 -C.sub.n) has first and second terminals. The first terminal of each capacitor may be coupled to a first circuit node (11) or to a first reference terminal (13). Likewise, the second terminal of each capacitor may be coupled to a second circuit node (12) or to a second reference terminal (14). One or more capacitors of the array of capacitors (C.sub.0 -C.sub.n) may be selectively coupled across the first (11) and second (12) circuit nodes or coupled across the first (13) and second (14) reference terminals, thereby permitting each capacitor to be electrically isolated from the array of capacitors (C.sub.0 -C.sub.n).

Abstract: A circuit and method for reducing voltage error when charging and discharging a storage capacitor (44) through a transmission gate (43). The storage capacitor (44) stores or holds a voltage coupled through the transmission gate (43) when the transmission gate (43) is disabled. The circuit comprises a clock generation circuit (47) providing complementary clock signals for enabling and disabling the transmission gate (43) and a charge negating transmission gate (46). The clock generation circuit (47) provides the complementary clock signals simultaneously to the transmission gates (43, 46). Alternate paths for dissipating channel charge of the transistors which comprise the transmission gate (43) are not formed by providing the complementary clock signals simultaneously. The channel charge is then canceled by the charge negating transmission gate (46) reducing voltage error on the storage capacitor (44).

Abstract: A circuit and method for reducing voltage error when charging and discharging a variable capacitor (44) through a switch (43). The switch (43) comprises a plurality of transmission gates (53-55) coupled in parallel. A control circuit (42) provides control signals for enabling transmission gates of the plurality of transmission gates (53-55). The control circuit (42) changes the resistance of the switch (43) by selecting an appropriate transmission gate wherein each transmission gate has a different resistance. The resistance of the switch (43) is varied as a capacitance of the variable capacitor (44) is changed to maintain a predetermined RC time constant over the entire range of capacitor values of the variable capacitor (44).