Patents by Inventor Danny L. Rose

Danny L. Rose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Architecture, method(s) and circuitry for low power memories
    Patent number: 6674682
    Abstract: A method for providing at least 2 Meg of SRAM cells having a maximum average operating current of approximately 9.43 mA comprising the steps of (A) providing an address path configured to consume a maximum average operating current of approximately 2.38 mA, (B) providing one or more sense amplifiers configured to consume a maximum average operating current of approximately 0.91 mA, (C) providing one or more bitlines configured to consume a maximum average operating current of approximately 0.94 mA and (D) providing a Q path configured to consume a maximum average operating current of approximately 0.61 mA.
    Type: Grant
    Filed: July 19, 2002
    Date of Patent: January 6, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: Keith A. Ford, Iulian C. Gradinariu, Bogdan I. Georgescu, Sean B. Mulholland, John J. Silver, Danny L. Rose
  • Block redundancy in ultra low power memory circuits
    Patent number: 6535437
    Abstract: A circuit comprising a memory array and a logic circuit. The memory array may be configured to read or write data in response to (i) one or more enable signals and (ii) one or more control signals. The logic circuit may be configured to generate the enable signals in response to one or more address signals. De-assertion of one or more of the enable signals generally reduces current consumption in the memory array.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: March 18, 2003
    Assignee: Cypress Semiconductor Corp.
    Inventors: John J. Silver, Iulian C. Gradinariu, Bogdan I. Georgescu, Keith A. Ford, Sean B. Mulholland, Danny L. Rose
  • Architecture, method(s) and circuitry for low power memories
    Publication number: 20020191470
    Abstract: A method for providing at least 2 Meg of SRAM cells having a maximum average operating current of approximately 9.43 mA comprising the steps of (A) providing an address path configured to consume a maximum average operating current of approximately 2.38 mA, (B) providing one or more sense amplifiers configured to consume a maximum average operating current of approximately 0.91 mA, (C) providing one or more bitlines configured to consume a maximum average operating current of approximately 0.94 mA and (D) providing a Q path configured to consume a maximum average operating current of approximately 0.61 mA.
    Type: Application
    Filed: July 19, 2002
    Publication date: December 19, 2002
    Inventors: Keith A. Ford, Iulian C. Gradinariu, Bogdan I. Georgescu, Sean B. Mulholland, John J. Silver, Danny L. Rose
  • Architecture, method (s) and circuitry for low power memories
    Patent number: 6493283
    Abstract: A circuit comprising a plurality of groups of memory cells and a control circuit. The plurality of groups of memory cells may each (i) have a first and a second bitline and (ii) configured to read and write data to one or more of the plurality of groups of memory cells. The control circuit may be configured to select an active group of the plurality of groups in response to one or more control signals. The control circuit may be implemented within the groups of memory cells.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: December 10, 2002
    Assignee: Cypress Semiconductor Corp.
    Inventors: Keith A. Ford, Iulian C. Gradinariu, Bogdan I. Georgescu, Sean B. Mulholland, John J. Silver, Danny L. Rose
  • Block redundancy in ultra low power memory circuits
    Patent number: 6249464
    Abstract: A circuit comprising a memory array and a logic circuit. The memory array may be configured to read or write data in response to (i) one or more enable signals and (ii) a global signal. The logic circuit may be configured to generate the enable signals in response to one or more address signals. De-assertion of the enable signals generally reduces current consumption in the memory array.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: June 19, 2001
    Assignee: Cypress Semiconductor Corp.
    Inventors: John J. Silver, Julian C. Gradinariu, Bogdan I. Georgescu, Keith A. Ford, Sean B. Mulholland, Danny L. Rose
  • Architecture, method(s) and circuitry for low power memories
    Patent number: 6163495
    Abstract: A circuit comprising a first and second bitline, a plurality of groups of memory cells and a control circuit. The first and second bitlines may each be configured to read and write to one or more of the plurality of groups of memory cells. Each of the plurality of bitline pairs may be interdigitated. The control circuit may be configured to select an active group of said plurality of groups in response to one or more control signals. The control circuit may be implemented within the groups of memory cells.
    Type: Grant
    Filed: September 17, 1999
    Date of Patent: December 19, 2000
    Assignee: Cypress Semiconductor Corp.
    Inventors: Keith A. Ford, Iulian C. Gradinariu, Bogdan I. Georgescu, Sean B. Mulholland, John J. Silver, Danny L. Rose