Abstract: A non-volatile memory cell (81) includes a drain-side select transistor (86), a source-side select transistor (87), and a storage transistor (88). The drain-side select transistor (86) is adjacent to the drain of the storage transistor (88) to prevent drain-disturb events. The source-side select transistor (87) is adjacent to the source of the storage transistor (88) to prevent source-disturb events. The select gate (152) of the drain-side select transistor (86), the select gate (143) of the source-side select transistor (87), and the floating gate (147) of the storage transistor (88) are formed on a dielectric layer (123) having a uniform thickness.

Abstract: An EEPROM cell (40) includes a floating gate transistor (47) and an isolation transistor (45). Both a floating gate (48) and an isolation gate (46) are formed on a tunnel dielectric (44) within the cell. The isolation gate is coupled to a doped source region (52) of the floating gate transistor. The isolation transistor is not biased during a program operation of the cell, enabling a thin tunnel dielectric (less than 120 angstroms) to be used beneath all portions of both gates within the cell. Thus, the need for both a conventional tunnel dielectric and a gate dielectric is eliminated. The cell tolerates over-erasure, can be programmed at low programming voltages, and has good current drive due to the thin tunnel dielectric throughout the cell.