Abstract: A unit cell for a prefabricated semiconductor chip, to be converted into an array of logic gates by selective metallization, comprises two complementary pairs of MOSFETs occupying respective quadrants of a rectangular substrate area, with external gate contacts disposed in respective headers extending along the minor sides of the rectangle. Each header further contains two external channel (source or drain) contacts which with the two external gate contacts form a group of four input/output contacts. Two metallic strips serving as supply buses, parallel to the minor sides, are separated from the two headers by relatively narrow substrate zones so as to define a relatively wide central region between them.