Abstract: This document discusses among other things, a system comprising a host controller, an Input/Output buffer, and a memory device. The memory device is coupled to the host controller and is configured to receive a read command from the host controller. The non-volatile includes an interface control logic, which is in communication with a non-volatile memory. The interface control logic includes a latency programming circuit coupled to the non-volatile memory and the Input/Output buffer. The latency programming circuit stores at least one value corresponding to dummy byte delays to be provided at the non-volatile memory prior to transferring data from the non-volatile memory during a read operation.

Abstract: A method of recovering overerased bits in a memory cell. In the method, a pair of reference currents are internally generated to define a current window corresponding to the erased state of the memory cell. The first reference current defines the highest current of the current window and the second reference current defines the lowest current of the current window. Then, it is determined which of the memory cells in a memory array are in an overerased state by having an amount of charge on its floating gate that corresponds to a conduction current during a read operation that is greater than the first reference current. Then, the overerased cells are programmed until the cells are in the erased state.

Abstract: A method of programming a multi-level memory chip in which the first, or lowest, voltage memory state through the next-to-last voltage memory state are programmed by a plurality of programming pulses increasing incrementally in voltage, alternated with a plurality of verify pulses, and in which the last, or highest, voltage memory state of the memory cell is programmed with a programming pulse of the threshold voltage required for charging the memory cell to the highest voltage memory state. The programming method provides accuracy in programming the intermediate memory states of the cell, while providing speed in programming the last memory state of the cell to increase the overall speed of the programming the memory cell.

Abstract: A method of recovering overerased bits in a memory cell. In the method, a pair of reference currents are internally generated to define a current window corresponding to the erased state of the memory cell. The first reference current defines the highest current of the current window and the second reference current defines the lowest current of the current window. Then, it is determined which of the memory cells in a memory array are in an overerased state by having an amount of charge on its floating gate that corresponds to a conduction current during a read operation that is greater than the first reference current. Then, the overerased cells are programmed until the cells are in the erased state.

Abstract: A method of programming a multi-level memory chip in which the first, or lowest, voltage memory state through the next-to-last voltage memory state are programmed by a plurality of programming pulses increasing incrementally in voltage, alternated with a plurality of verify pulses, and in which the last, or highest, voltage memory state of the memory cell is programmed with a programming pulse of the threshold voltage required for charging the memory cell to the highest voltage memory state. The programming method provides accuracy in programming the intermediate memory states of the cell, while providing speed in programming the last memory state of the cell to increase the overall speed of the programming the memory cell.

Abstract: A row decoder circuit for use in programming a memory device. The row decoder circuit includes a means for selecting the wordline of a memory cell to be programmed and a wordline driver circuit that switches between a first power supply line that supplies a programming voltage and a second power supply line that supplies a read/verify voltage in order to provide either the programming voltage or the read/verify voltage to the gate of a selected memory cell on the wordline. This switching between programming and read/verify voltages results in the programming pulses used to program the selected memory cell. The present invention allows for shorter programming pulses to be used and provides faster speed in the overall programming of the memory cell.

Abstract: In order to establish boundary current levels for more than two memory states, a circuit is provided that uses reference currents defining the center of each state. The reference currents are defined by multiple pre-programmed reference memory cells or by a single reference memory cell together with a current mirror that sets the other reference currents at specified proportions of a first reference current. With these reference currents, an analog circuit block generates fractional currents at (1−m) and m of the reference currents, where m is a specified margin value equal to 50% for read operations and less than 50% for program verify operations, then combines fractional currents for adjacent states to produce the boundary current levels. The fractional currents may be obtained with pairs of current mirrors biased by sense amplifiers for the various reference currents.