Patents by Inventor Dany Davidov
Dany Davidov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230388241Abstract: An apparatus includes an interface circuit and an encoder circuit. The interface circuit is configured to send a data packet via a plurality of segments, and to send an idle value via the plurality of segments when no data packet is available. The idle value is configured to cause a segment in a receiving apparatus to idle. The encoder circuit is configured to receive a particular data packet, and, if a portion of the particular data packet has a same value as the idle value for a subset of the plurality of segments, to replace at least a portion of the data packet with a mask value to generate a modified data packet. The mask value indicates how to recreate the particular data packet. The encoder circuit is further configured to send the modified data packet to the receiving apparatus via the plurality of segments of the interface circuit.Type: ApplicationFiled: May 31, 2023Publication date: November 30, 2023Inventors: Dany Davidov, Nir Leshem, Mark Pilip, Sergio Kolor
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Patent number: 11803471Abstract: An integrated circuit (IC) including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. For example, the IC may include an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices; and an off-chip interconnect coupled to the interconnect fabric and configured to couple the interconnect fabric to a corresponding interconnect fabric on another instance of the integrated circuit, wherein the interconnect fabric and the off-chip interconnect provide an interface that transparently connects the one or more memory controller circuits, the processor cores, graphics processing units, and peripheral devices in either a single instance of the integrated circuit or two or more instances of the integrated circuit.Type: GrantFiled: August 22, 2022Date of Patent: October 31, 2023Assignee: Apple Inc.Inventors: Per H. Hammarlund, Lior Zimet, Sergio Kolor, Sagi Lahav, James Vash, Gaurav Garg, Tal Kuzi, Jeffry E. Gonion, Charles E. Tucker, Lital Levy-Rubin, Dany Davidov, Steven Fishwick, Nir Leshem, Mark Pilip, Gerard R. Williams, III, Harshavardhan Kaushikkar, Srinivasa Rangan Sridharan
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Patent number: 11706150Abstract: An apparatus includes an interface circuit and an encoder circuit. The interface circuit is configured to send a data packet via a plurality of segments, and to send an idle value via the plurality of segments when no data packet is available. The idle value is configured to cause a segment in a receiving apparatus to idle. The encoder circuit is configured to receive a particular data packet, and, if a portion of the particular data packet has a same value as the idle value for a subset of the plurality of segments, to replace at least a portion of the data packet with a mask value to generate a modified data packet. The mask value indicates how to recreate the particular data packet. The encoder circuit is further configured to send the modified data packet to the receiving apparatus via the plurality of segments of the interface circuit.Type: GrantFiled: April 6, 2021Date of Patent: July 18, 2023Assignee: Apple Inc.Inventors: Dany Davidov, Nir Leshem, Mark Pilip, Sergio Kolor
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Publication number: 20230214350Abstract: A system includes a plurality of systems-on-a-chip (SoCs), connected by a network. The plurality of SoCs and the network are configured to operate as a single logical computing system. The plurality of SoCs may be configured to exchange local power information indicative of network activity occurring on their respective portions of the network. A given one of the plurality of SoCs may be configured to determine that a local condition for placing the respective portion of the network corresponding to the given SoC into a reduced power mode has been satisfied. The given SoC may be further configured to place the respective portion of the network into the reduced power mode in response to determining that a global condition for the reduced power mode is satisfied. The global condition may be assessed based upon current local power information for remaining ones of the plurality of SoCs.Type: ApplicationFiled: February 27, 2023Publication date: July 6, 2023Inventors: Dany Davidov, Misbah Ramadan, Itamar Rozen, Tzach Zemer
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Patent number: 11592889Abstract: A system includes a plurality of systems-on-a-chip (SoCs), connected by a network. The plurality of SoCs and the network are configured to operate as a single logical computing system. The plurality of SoCs may be configured to exchange local power information indicative of network activity occurring on their respective portions of the network. A given one of the plurality of SoCs may be configured to determine that a local condition for placing the respective portion of the network corresponding to the given SoC into a reduced power mode has been satisfied. The given SoC may be further configured to place the respective portion of the network into the reduced power mode in response to determining that a global condition for the reduced power mode is satisfied. The global condition may be assessed based upon current local power information for remaining ones of the plurality of SoCs.Type: GrantFiled: May 12, 2021Date of Patent: February 28, 2023Assignee: Apple Inc.Inventors: Dany Davidov, Misbah Ramadan, Itamar Rozen, Tzach Zemer
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Publication number: 20230058989Abstract: An integrated circuit (IC) including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. For example, the IC may include an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices; and an off-chip interconnect coupled to the interconnect fabric and configured to couple the interconnect fabric to a corresponding interconnect fabric on another instance of the integrated circuit, wherein the interconnect fabric and the off-chip interconnect provide an interface that transparently connects the one or more memory controller circuits, the processor cores, graphics processing units, and peripheral devices in either a single instance of the integrated circuit or two or more instances of the integrated circuit.Type: ApplicationFiled: August 22, 2022Publication date: February 23, 2023Inventors: Per H. Hammarlund, Lior Zimet, Sergio Kolor, Sagi Lahav, James Vash, Gaurav Garg, Tal Kuzi, Jeffry E. Gonion, Charles E. Tucker, Lital Levy-Rubin, Dany Davidov, Steven Fishwick, Nir Leshem, Mark Pilip, Gerard R. Williams, III, Harshavardhan Kaushikkar, Srinivasan Rangan Sridharan
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Publication number: 20220365579Abstract: A system includes a plurality of systems-on-a-chip (SoCs), connected by a network. The plurality of SoCs and the network are configured to operate as a single logical computing system. The plurality of SoCs may be configured to exchange local power information indicative of network activity occurring on their respective portions of the network. A given one of the plurality of SoCs may be configured to determine that a local condition for placing the respective portion of the network corresponding to the given SoC into a reduced power mode has been satisfied. The given SoC may be further configured to place the respective portion of the network into the reduced power mode in response to determining that a global condition for the reduced power mode is satisfied. The global condition may be assessed based upon current local power information for remaining ones of the plurality of SoCs.Type: ApplicationFiled: May 12, 2021Publication date: November 17, 2022Inventors: Dany Davidov, Misbah Ramadan, Itamar Rozen, Tzach Zemer
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Publication number: 20220321490Abstract: An apparatus includes an interface circuit and an encoder circuit. The interface circuit is configured to send a data packet via a plurality of segments, and to send an idle value via the plurality of segments when no data packet is available. The idle value is configured to cause a segment in a receiving apparatus to idle. The encoder circuit is configured to receive a particular data packet, and, if a portion of the particular data packet has a same value as the idle value for a subset of the plurality of segments, to replace at least a portion of the data packet with a mask value to generate a modified data packet. The mask value indicates how to recreate the particular data packet. The encoder circuit is further configured to send the modified data packet to the receiving apparatus via the plurality of segments of the interface circuit.Type: ApplicationFiled: April 6, 2021Publication date: October 6, 2022Inventors: Dany Davidov, Nir Leshem, Mark Pilip, Sergio Kolor
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Publication number: 20220284163Abstract: A system includes a first instance and a second instance of an integrated circuit. The integrated circuits include respective external interfaces with a physical pin layout having transmit and receive pins for a particular bus located in complementary positions relative to an axis of symmetry. The external interfaces of the first and second instances of the integrated circuit are positioned such that the transmit and receive pins for the given I/O signal on the first instance are aligned, respectively, with the receive and transmit pins for the given I/O signal on the second instance.Type: ApplicationFiled: March 5, 2021Publication date: September 8, 2022Inventors: Sergio Kolor, Dany Davidov, Nir Leshem, Mark Pilip