Abstract: A semiconductor device includes first and second wells formed side by side as impurity diffusion regions of a first conductive type in a semiconductor substrate, below an intermediate dielectric film that covers a major surface of the substrate. A conductive layer formed above the intermediate dielectric film is held at a potential. A first resistive layer is formed on the intermediate dielectric film and is electrically connected to the first well. A second resistive layer is formed on the intermediate dielectric film and is electrically connected to the second well. The first resistive layer and first well form a first resistance element. The second resistive layer and second well form a second resistance element.

Abstract: A semiconductor device includes first and second wells formed side by side as impurity diffusion regions of a first conductive type in a semiconductor substrate, below an intermediate dielectric film that covers a major surface of the substrate. A conductive layer formed above the intermediate dielectric film is held at a potential. A first resistive layer is formed on the intermediate dielectric film and is electrically connected to the first well. A second resistive layer is formed on the intermediate dielectric film and is electrically connected to the second well. The first resistive layer and first well form a first resistance element. The second resistive layer and second well form a second resistance element.

Abstract: A current cell matrix type of digital-to-analog (D/A) converter to prevent deterioration of a.c. characteristics on a current path for digital-to-analog conversion includes a array of current source cells arranged in a matrix configuration. Each current source cell includes a current source transistor to generate the cell current. During the regular operation, the cell current is flowed on output lines via a first transistor connected in cascode to the current source transistor. During the calibration operation, the cell current is flowed into a current comparator via a second transistor connected in cascode to the current source transistor. This prevents parasitic capacitance from being additively caused in switches for the first transistor and in another switch for the second transistor to prevent deterioration of a.c. characteristics on the current path.

Abstract: A reference current generator circuit that suppresses variations in the production of parts and attains a voltage reduction, thereby suppressing power consumption. The reference current generator circuit includes current generating circuit parts, differential amplifying circuit parts, output circuit parts that output first and second reference currents respectively, and a resistor for converting a reference current to a reference voltage. Since respective voltages are kept at the same potential, respective PMOSs are operated in a linear region by means of the differential amplifying circuit pads.

Abstract: A reference current circuit includes a differential amplifier amplifying a difference in potential between a reference voltage and a first node and outputting the amplified potential difference to a second node, and adjusting transistors connected between a supply voltage and the first node. The reference current circuit further includes switches provided correspondingly to the adjusting transistors to apply a voltage of the second node to control electrodes of the adjusting transistors in response to control signals that are respectively input to the switches. The reference current circuit further includes a resistance connected between the first node and a common potential, and an output transistor having its conduction state responsive to the voltage of the second node for controlling a current supplied from the supply voltage to a load.

Abstract: A current cell matrix type of digital-to-analog (D/A) converter to prevent deterioration of a.c. characteristics on a current path for digital-to-analog conversion includes a array of current source cells arranged in a matrix configuration. Each current source cell includes a current source transistor to generate the cell current. During the regular operation, the cell current is flowed on output lines via a first transistor connected in cascode to the current source transistor. During the calibration operation, the cell current is flowed into a current comparator via a second transistor connected in cascode to the current source transistor. This prevents parasitic capacitance from being additively caused in switches for the first transistor and in another switch for the second transistor to prevent deterioration of a.c. characteristics on the current path.

Abstract: A reference current circuit includes a differential amplifier amplifying a difference in potential between a reference voltage and a first node and outputting the amplified potential difference to a second node, and adjusting transistors connected between a supply voltage and the first node. The reference current circuit further includes switches provided correspondingly to the adjusting transistors to apply a voltage of the second node to control electrodes of the adjusting transistors in response to control signals that are respectively input to the switches. The reference current circuit further includes a resistance connected between the first node and a common potential, and an output transistor having its conduction state responsive to the voltage of the second node for controlling a current supplied from the supply voltage to a load.

Abstract: A comparator includes: a CMOS inverter constituted by a combination of a first p-channel MOS transistor and a first n-channel MOS transistor; a second p-channel MOS transistor connected in parallel to the first p-channel MOS transistor in an analog input period, and disconnected from the first p-channel MOS transistor in a comparison period; and a second n-channel MOS transistor connected in parallel to the first n-channel MOS transistor in the analog input period, and disconnected from the first n-channel MOS transistor in the comparison period.

Abstract: The present invention provides a reference current generator circuit that suppresses variations in the production of parts and attains a voltage reduction, thereby suppressing power consumption. The reference current generator circuit comprises current generating circuit parts, differential amplifying circuit parts, output circuit parts that output first and second reference currents respectively, and a resistor for converting a reference current to a reference voltage. Since respective voltages are kept at the same potential, respective PMOSs are operated in a linear region by means of the differential amplifying circuit parts.

Abstract: A digital signal processing unit includes a control unit and a data computing unit. An R/L register for distinguishing independent data is disposed in the control unit. An R/L select signal for indicating independent data is supplied to the data computing unit. A data processing instruction signal for distinguishing a data processing instruction from other instructions is issued from an instruction decoder. The R/L register for distinguishing independent data is controlled by the data processing instruction signal. In the data computing unit, the portion related to storing independent data is multiplexed according to the number of independent data to be processed, and this multiplexed portion is controlled by the R/L select signal supplied from the control unit.

Abstract: A comparator includes: a CMOS inverter constituted by a combination of a first p-channel MOS transistor and a first n-channel MOS transistor; a second p-channel MOS transistor connected in parallel to the first p-channel MOS transistor in an analog input period, and disconnected from the first p-channel MOS transistor in a comparison period; and a second n-channel MOS transistor connected in parallel to the first n-channel MOS transistor in the analog input period, and disconnected from the first n-channel MOS transistor in the comparison period.

Abstract: A digital signal processing unit includes a control unit and a data computing unit. An R/L register for distinguishing independent data is disposed in the control unit. An R/L select signal for indicating independent data is supplied to the data computing unit. A data processing instruction signal for distinguishing a data processing instruction from other instructions is issued from an instruction decoder. The R/L register for distinguishing independent data is controlled by the data processing instruction signal. In the data computing unit, the portion related to storing independent data is multiplexed according to the number of independent data to be processed, and this multiplexed portion is controlled by the R/L select signal supplied from the control unit.