Patents by Inventor Danyu Zhu

Danyu Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • I/O completion polling for low latency storage device
    Patent number: 10776289
    Abstract: An I/O processing system includes reception of a request to perform an I/O operation from a user-mode application, providing of the request to a storage device, scheduling of an operating system deferred procedure call to determine whether the storage device has completed the I/O operation, execution of the scheduled deferred procedure call to determine that the storage device has completed the I/O operation, and transmission of a return corresponding to the completed I/O operation to the user-mode application.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: September 15, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Xiaozhong Xing, Liang Yang, Danyu Zhu, Robin Andrew Alexander, HoYuen Chau, Vishal Jose Mannanal
  • Timer-based I/O completion polling for low latency storage device
    Patent number: 10740258
    Abstract: An I/O processing system includes reception of a request to perform an I/O operation at a storage driver, and, in response to receiving the request, providing of the request to a storage device, and scheduling a timer associated with a callback routine to determine whether the storage device has completed the I/O operation, and, in response to expiration of the scheduled timer, determination of whether the storage device has completed the I/O operation.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: August 11, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Robin Andrew Alexander, HoYuen Chau, Xiaozhong Xing, Danyu Zhu, Liang Yang, Vishal Jose Mannanal
  • TIMER-BASED I/O COMPLETION POLLING FOR LOW LATENCY STORAGE DEVICE
    Publication number: 20200125504
    Abstract: An I/O processing system includes reception of a request to perform an I/O operation at a storage driver, and, in response to receiving the request, providing of the request to a storage device, and scheduling a timer associated with a callback routine to determine whether the storage device has completed the I/O operation, and, in response to expiration of the scheduled timer, determination of whether the storage device has completed the I/O operation.
    Type: Application
    Filed: October 23, 2018
    Publication date: April 23, 2020
    Inventors: Robin Andrew ALEXANDER, HoYuen CHAU, Xiaozhong XING, Danyu ZHU, Liang YANG, Vishal JOSE MANNANAL
  • I/O COMPLETION POLLING FOR LOW LATENCY STORAGE DEVICE
    Publication number: 20200097419
    Abstract: An I/O processing system includes reception of a request to perform an I/O operation from a user-mode application, providing of the request to a storage device, scheduling of an operating system deferred procedure call to determine whether the storage device has completed the I/O operation, execution of the scheduled deferred procedure call to determine that the storage device has completed the I/O operation, and transmission of a return corresponding to the completed I/O operation to the user-mode application.
    Type: Application
    Filed: October 23, 2018
    Publication date: March 26, 2020
    Inventors: Xiaozhong XING, Liang YANG, Danyu ZHU, Robin Andrew ALEXANDER, HoYuen CHAU, Vishal JOSE MANNANAL
  • Latency sensitive software interrupt and thread scheduling
    Patent number: 8943252
    Abstract: Various embodiments provide an ability to schedule latency-sensitive tasks based, at least in part, upon one or more processor cores usage metrics. Some embodiments gather information associated with whether one or more processor cores are in a heavily loaded state. Alternately or additionally, some embodiments gather information identifying latency-sensitive tasks. Task(s) can be (re)assigned to different processor core(s) for execution when it has been determined that an originally assigned processor core has exceeded a usage threshold.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: January 27, 2015
    Assignee: Microsoft Corporation
    Inventors: Bradley M. Waters, Danyu Zhu
  • Latency Sensitive Software Interrupt and Thread Scheduling
    Publication number: 20140052882
    Abstract: Various embodiments provide an ability to schedule latency-sensitive tasks based, at least in part, upon one or more processor cores usage metrics. Some embodiments gather information associated with whether one or more processor cores are in a heavily loaded state. Alternately or additionally, some embodiments gather information identifying latency-sensitive tasks. Task(s) can be (re)assigned to different processor core(s) for execution when it has been determined that an originally assigned processor core has exceeded a usage threshold.
    Type: Application
    Filed: August 16, 2012
    Publication date: February 20, 2014
    Applicant: MICROSOFT CORPORATION
    Inventors: Bradley M. Waters, Danyu Zhu