Abstract: A non-volatile memory device includes a memory cell array from which data is read via a plurality of bitlines, which includes a plurality of memory cells having gates respectively connected with a plurality of wordlines, a first type global wordline decoder configured to selectively apply n different voltages, where n is an integer greater than or equal to 3, to a corresponding wordline of the plurality of wordlines in a program mode, and a second type global wordline decoder configured to selectively apply (n?1) different voltages to a corresponding wordline of the plurality of wordlines in the program mode, the second type global wordline decoder having fewer switching elements than the first type global wordline decoder.