Patents by Inventor Dao-Ping Wang
Dao-Ping Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230197144Abstract: An adaptive control circuit of SRAM (Static Random Access Memory) includes a switch circuit, a forward diode-connected transistor, a backward diode-connected transistor, and a first delay circuit. The switch circuit is supplied by a supply voltage, and is coupled to a first node. The backward diode-connected transistor is coupled in parallel with the forward diode-connected transistor between the first node and a second node. The first delay circuit is coupled between the second node and a ground voltage.Type: ApplicationFiled: September 29, 2022Publication date: June 22, 2023Inventor: Dao-Ping WANG
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Patent number: 10176853Abstract: A pre-processing circuit is used for pre-processing a data-line voltage representative of a data output of a memory device. The pre-processing circuit includes a pre-charging circuit and a clamping circuit. The pre-charging circuit pre-charges a data line to adjust the data-line voltage at the data line that is coupled to the memory device. The clamping circuit clamps the data-line voltage to generate a clamped data-line voltage when the data-line voltage is pre-charged to a level that enables a clamping function of the clamping circuit, wherein the clamped data-line voltage is lower than a supply voltage of the pre-processing circuit. The clamping circuit includes a feedback circuit that feeds back a control voltage according to the data-line voltage at the data line, and further reduces its direct current (DC) leakage when the data-line voltage is clamped, wherein the clamping function of the clamping circuit is controlled by the control voltage.Type: GrantFiled: April 27, 2017Date of Patent: January 8, 2019Assignee: MEDIATEK INC.Inventors: Chi-Hao Hong, Dao-Ping Wang, Yi-Wei Chen, Yi-Ping Kuo, Shu-Lin Lai
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Publication number: 20170345469Abstract: A pre-processing circuit is used for pre-processing a data-line voltage representative of a data output of a memory device. The pre-processing circuit includes a pre-charging circuit and a clamping circuit. The pre-charging circuit pre-charges a data line to adjust the data-line voltage at the data line that is coupled to the memory device. The clamping circuit clamps the data-line voltage to generate a clamped data-line voltage when the data-line voltage is pre-charged to a level that enables a clamping function of the clamping circuit, wherein the clamped data-line voltage is lower than a supply voltage of the pre-processing circuit. The clamping circuit includes a feedback circuit that feeds back a control voltage according to the data-line voltage at the data line, and further reduces its direct current (DC) leakage when the data-line voltage is clamped, wherein the clamping function of the clamping circuit is controlled by the control voltage.Type: ApplicationFiled: April 27, 2017Publication date: November 30, 2017Inventors: Chi-Hao Hong, Dao-Ping Wang, Yi-Wei Chen, Yi-Ping Kuo, Shu-Lin Lai
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Patent number: 9640229Abstract: A memory circuit includes a transistor, a signal line and a plurality of information lines. The transistor includes a first electrode, a second electrode and a control electrode. The transistor is included in a memory cell. The signal line is connected to the first electrode of the transistor. The voltage on the signal line is programmable. At most one of the information lines is connected to the second electrode of the transistor via a contact. Information stored in the memory cell is coded according to the voltage programmed on the signal line and an option of which information line the contact should connect to the second electrode of the transistor.Type: GrantFiled: April 21, 2015Date of Patent: May 2, 2017Assignee: MEDIATEK INC.Inventors: Dao-Ping Wang, Chia-Wei Wang
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Publication number: 20160203847Abstract: A memory circuit includes a transistor, a signal line and a plurality of information lines. The transistor includes a first electrode, a second electrode and a control electrode. The transistor is included in a memory cell. The signal line is connected to the first electrode of the transistor. The voltage on the signal line is programmable. At most one of the information lines is connected to the second electrode of the transistor via a contact. Information stored in the memory cell is coded according to the voltage programmed on the signal line and an option of which information line the contact should connect to the second electrode of the transistor.Type: ApplicationFiled: April 21, 2015Publication date: July 14, 2016Inventors: Dao-Ping WANG, Chia-Wei WANG
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Patent number: 9142285Abstract: A multi-port SRAM with shared write bit-line architecture and selective read path for low power operation includes a first memory cell, a second memory cell, and a common switch set. The second memory cell makes use of the common switch set to share the A-port write bit-line and the B-port write bit-line with the first memory cell so as to reduce half write bit-line number and reduce the write current consumption caused by pre-charging the bit-line to VDD. It also provides a selective read path structure for read operation. Replacing the ground connection in the read port with a virtual VSS controlled by a Y-select signal reduces read-port current consumption.Type: GrantFiled: December 13, 2013Date of Patent: September 22, 2015Assignee: NATIONAL CHIAO TUNG UNIVERSITYInventors: Wei Hwang, Dao-Ping Wang
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Publication number: 20150170734Abstract: A multi-port SRAM with shared write bit-line architecture and selective read path for low power operation includes a first memory cell, a second memory cell, and a common switch set. The second memory cell makes use of the common switch set to share the A-port write bit-line and the B-port write bit-line with the first memory cell so as to reduce half write bit-line number and reduce the write current consumption caused by pre-charging the bit-line to VDD. It also provides a selective read path structure for read operation. Replacing the ground connection in the read port with a virtual VSS controlled by a Y-select signal reduces read-port current consumption.Type: ApplicationFiled: December 13, 2013Publication date: June 18, 2015Applicant: National Chiao Tung UniversityInventors: Wei HWANG, Dao-Ping WANG
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Patent number: 8891289Abstract: A 10-transistor dual-port SRAM with shared bit-line architecture includes a first memory cell and a second memory cell. The first memory cell has a first storage unit, a first switch set, and a second switch set. The second memory cell has a second storage unit, a third switch set, and a fourth switch set. The second switch set is coupled to a complement first A-port bit line and a complement first B-port bit line, and connected to the first storage unit. The third switch set is connected to a complement second A-port bit line, a complement second B-port bit line, and the second storage unit. Thus, the second memory cell can make use of the third switch set to share the complement first A-port bit line and the complement first B-port bit line with the first memory cell.Type: GrantFiled: April 24, 2013Date of Patent: November 18, 2014Assignee: National Chiao Tung UniversityInventors: Wei Hwang, Dao-Ping Wang
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Publication number: 20140198562Abstract: A 10-transistor dual-port SRAM with shared bit-line architecture includes a first memory cell and a second memory cell. The first memory cell has a first storage unit, a first switch set, and a second switch set. The second memory cell has a second storage unit, a third switch set, and a fourth switch set. The second switch set is coupled to a complement first A-port bit line and a complement first B-port bit line, and connected to the first storage unit. The third switch set is connected to a complement second A-port bit line, a complement second B-port bit line, and the second storage unit. Thus, the second memory cell can make use of the third switch set to share the complement first A-port bit line and the complement first B-port bit line with the first memory cell.Type: ApplicationFiled: April 24, 2013Publication date: July 17, 2014Applicant: National Chiao Tung UniversityInventors: Wei HWANG, Dao-Ping WANG
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Patent number: 7701755Abstract: A memory includes a plurality of cells arranged in a matrix having a plurality of rows and a plurality of columns, wherein each cell is capable of storing a bit. Each cell is coupled between a first power supply node that receives a power supply voltage and a second power supply node that receives a second voltage. A plurality of word lines are associated with the memory cells and supplied by a third voltage in read or write operation. The third voltage is a suppressed power supply voltage. The second voltage is negative in read operation and positive in write operation.Type: GrantFiled: January 2, 2007Date of Patent: April 20, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yen-Huei Chen, Hung-Jen Liao, Kun-Lung Chen, Yung-Lung Lin, Dao-Ping Wang
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Patent number: 7577052Abstract: A power control circuit for an integrated circuit module includes at least one switch device coupled between a supply voltage and a power node of the integrated circuit module; and a switch control module having a first terminal coupled to the switch device, a second terminal coupled to a control signal, a third terminal coupled to a first storage node of at least one tracking cell, a fourth terminal coupled to a second storage node of the tracking cell, and a fifth terminal coupled to the power node of the integrated circuit module, for controlling the switch device to pass the supply voltage to the power node with or without a substantial voltage drop depending on an operation mode of the integrated circuit module.Type: GrantFiled: December 13, 2006Date of Patent: August 18, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jui-Jen Wu, Kun-Lung Chen, Hung-Jen Liao, Yung-Lung Lin, Chen Yen-Huei, Dao-Ping Wang
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Patent number: 7535788Abstract: A writing dynamic power control circuit is disclosed, which comprises a BL and its complementary BLB, at least one memory cell coupled to both the BL and BLB, a first NMOS transistor having a source, a drain and a gate coupled to the BL, the Vss and a first data signal, respectively, a second NMOS transistor having a source, a drain and a gate coupled to the BLB, the Vss and a second data signal, respectively, wherein the second data signal is complementary to the first data signal, a first PMOS transistor having a source, a drain and a gate coupled to a high voltage power supply (CVDD) node, the BLB and the BL, respectively, and a second PMOS transistor having a source, a drain and a gate coupled to the CVDD node, the BL and the BLB, respectively.Type: GrantFiled: December 8, 2006Date of Patent: May 19, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jui-Jen Wu, Kun-Lung Chen, Hung-Jen Liao, Yung-Lung Lin, Chen Yen-Huei, Dao-Ping Wang
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Patent number: 7505319Abstract: The disclosure generally relates to a method and apparatus for a high efficiency redundancy scheme for a memory system. In one embodiment, the disclosure relates to a memory circuit having: a memory array defined by a plurality of memory cells arranged in one or more columns and one or more rows, each memory cell communicating with one of a pair of complementary bit-lines and with a word-line; a plurality of IO circuits, each IO circuit associated with one of the plurality of memory cell columns; a plurality of redundant bit-lines, each redundant bit line communicating with a redundant bit cell; a first circuit for detecting a defective memory cell in said memory circuit; a second circuit for selecting one of the plurality of redundant bit-lines for switching from the failed memory cell to the redundant memory cell; and a third circuit for directing a word-line pulse of said defective memory cell to said selected redundant memory cell.Type: GrantFiled: January 31, 2007Date of Patent: March 17, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Jen Wu, Yung-Lung Lin, Yen-Huei Chen, Dao-Ping Wang
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Patent number: 7468903Abstract: A system and method for writing a SRAM cell coupled to complimentary first and second bit-lines (BLs) is disclosed, the method comprising asserting a word-line (WL) selecting the SRAM cell to a first positive voltage, providing a second positive voltage at the first BL, providing a first negative voltage at the second BL, and asserting a plurality of WLs not selecting the SRAM cell to a second negative voltage, wherein the writing margin of the SRAM cell is increased.Type: GrantFiled: November 13, 2006Date of Patent: December 23, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Dao-Ping Wang, Hung-Jen Liao, Kun Lung Chen, Yung-Lung Lin, Jui-Jen Wu, Chen Yen-Huei
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Patent number: 7420835Abstract: The present invention relates generally to an integrated circuit (IC) design, and more particularly to a method and apparatus for providing an SRAM cell with improved read and write margins. The method includes providing a first negative voltage to a bit-line and a supply voltage to an inverse bit-line to increase a first potential difference between the bit-line and the inverse bit-line during a write operation of a logic “0.” The method also includes providing the first negative voltage to the inverse bit-line and the supply voltage to the bit-line to increase the first potential difference during a write operation of a data “1.Type: GrantFiled: November 30, 2006Date of Patent: September 2, 2008Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Dao-Ping Wang, Ping-Wei Wang
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Publication number: 20080184064Abstract: The disclosure generally relates to a method and apparatus for a high efficiency redundancy scheme for a memory system. In one embodiment, the disclosure relates to a memory circuit having: a memory array defined by a plurality of memory cells arranged in one or more columns and one or more rows, each memory cell communicating with one of a pair of complementary bit-lines and with a word-line; a plurality of IO circuits, each IO circuit associated with one of the plurality of memory cell columns; a plurality of redundant bit-lines, each redundant bit line communicating with a redundant bit cell; a first circuit for detecting a defective memory cell in said memory circuit; a second circuit for selecting one of the plurality of redundant bit-lines for switching from the failed memory cell to the redundant memory cell; and a third circuit for directing a word-line pulse of said defective memory cell to said selected redundant memory cell.Type: ApplicationFiled: January 31, 2007Publication date: July 31, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jui-Jen Wu, Yung-Lung Lin, Yen-Huei Chen, Dao-Ping Wang
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Publication number: 20080158939Abstract: A memory includes a plurality of cells arranged in a matrix having a plurality of rows and a plurality of columns, wherein each cell is capable of storing a bit. Each cell is coupled between a first power supply node that receives a power supply voltage and a second power supply node that receives a second voltage. A plurality of word lines are associated with the memory cells and supplied by a third voltage in read or write operation. The third voltage is a suppressed power supply voltage. The second voltage is negative in read operation and positive in write operation.Type: ApplicationFiled: January 2, 2007Publication date: July 3, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Huei Chen, Hung-Jen Liao, Kun-Lung Chen, Jui-Jen Wu, Yung-Lung Lin, Dao-Ping Wang
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Publication number: 20080144419Abstract: A power control circuit for an integrated circuit module includes at least one switch device coupled between a supply voltage and a power node of the integrated circuit module; and a switch control module having a first terminal coupled to the switch device, a second terminal coupled to a control signal, a third terminal coupled to a first storage node of at least one tracking cell, a fourth terminal coupled to a second storage node of the tracking cell, and a fifth terminal coupled to the power node of the integrated circuit module, for controlling the switch device to pass the supply voltage to the power node with or without a substantial voltage drop depending on an operation mode of the integrated circuit module.Type: ApplicationFiled: December 13, 2006Publication date: June 19, 2008Inventors: Jui-Jen Wu, Kun-Lung Chen, Hung-Jen Liao, Yung-Lung Lin, Chen Yen-Huei, Dao-Ping Wang
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Publication number: 20080137449Abstract: A writing dynamic power control circuit is disclosed, which comprises a BL and its complementary BLB, at least one memory cell coupled to both the BL and BLB, a first NMOS transistor having a source, a drain and a gate coupled to the BL, the Vss and a first data signal, respectively, a second NMOS transistor having a source, a drain and a gate coupled to the BLB, the Vss and a second data signal, respectively, wherein the second data signal is complementary to the first data signal, a first PMOS transistor having a source, a drain and a gate coupled to a high voltage power supply (CVDD) node, the BLB and the BL, respectively, and a second PMOS transistor having a source, a drain and a gate coupled to the CVDD node, the BL and the BLB, respectively.Type: ApplicationFiled: December 8, 2006Publication date: June 12, 2008Inventors: Jui-Jen Wu, Kun-Lung Chen, Hung-Jen Liao, Yung-Lung Lin, Chen Yen-Huei, Dao-Ping Wang
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Publication number: 20080130380Abstract: The present invention relates generally to an integrated circuit (IC) design, and more particularly to a method and apparatus for providing an SRAM cell with improved read and write margins. The method includes providing a first negative voltage to a bit-line and a supply voltage to an inverse bit-line to increase a first potential difference between the bit-line and the inverse bit-line during a write operation of a logic “0.” The method also includes providing the first negative voltage to the inverse bit-line and the supply voltage to the bit-line to increase the first potential difference during a write operation of a data “1.Type: ApplicationFiled: November 30, 2006Publication date: June 5, 2008Inventors: Dao-Ping Wang, Ping-Wei Wang