Abstract: A semiconductor device includes a substrate of a first conductivity type and a tub of a second conductivity type formed in the substrate. The second conductivity type is opposite to the first conductivity type; and the tub has a tub bottom layer of the second conductivity type buried in an initial substrate layer of the substrate with a peak dopant concentration plane of the tub bottom layer substantially away from a top surface of the initial substrate layer for a predetermined buried depth that is essentially greater than 0.5 ?m. A transistor formed inside the tub in the substrate can have a breakdown voltage greater than 70V up to especially over 100V.

Abstract: A method for forming a semiconductor device having a tub. The method includes forming a substrate of a first conductivity type that includes a tub bottom layer of the tub. The tub bottom layer is of a second conductivity type that is opposite to the first conductivity type and has a tub bottom layer peak dopant concentration plane that is substantially away from a top surface of an initial substrate layer of the substrate for a predetermined tub bottom layer buried depth that is essentially greater than 0.5 ?m. The method can further include forming a plurality of tub sidewalls of the tub. The method can further include forming a high voltage transistor inside the tub.

Abstract: A LDMOS including a semiconductor substrate, a gate oxide, a gate, field plate oxide layers and field plate barrier layers is disclosed. A first field plate oxide layer and a second field plate oxide layer are positioned atop the gate oxide with a spacing between them. A first field plate barrier layer and a second field plate barrier layer are positioned atop the first and the second field plate oxide layers, respectively. A third field plate barrier layer is positioned atop the first and the second field plate barrier layers and the spacing. A third field plate oxide layer is positioned atop the third field plate barrier layer. The third field plate oxide layer includes a first portion positioned atop the first field plate oxide layer and a second portion positioned atop the spacing. A fourth field plate barrier layer is positioned atop the third field plate oxide layer.

Abstract: A lateral transistor having a well region, a body region, a source region, a drain region, a gate structure and a trenched Schottky barrier structure. The trenched Schottky barrier structure extended vertically from a top surface of the well region through the source region and the body region and penetrated into at least a portion of the well region to form a vertical Schottky contact.

Abstract: A semiconductor device includes a junction field effect transistor (JFET) device. The JFET device includes a substrate, a first well region, a first source region, a first drain region, a first gate region and a second gate region. A channel region is formed between the first source region and the first drain region along a first direction. The first gate region and the second gate region are located within the channel region, the first gate region includes a first surface extending from a top surface to a bottom surface of the first gate region, and the second gate region includes a second surface extending from a top surface to a bottom surface of the second gate region. The first surface is facing a second direction perpendicular to the first direction toward the second surface. A method of manufacturing such semiconductor device is also provided.

Abstract: A lateral diode with high breakdown voltage capability and a method for forming the lateral diode. The lateral diode has an anode, a cathode, a substrate having a first conductivity type, an epitaxial layer having formed on the substrate, a current region formed in the epitaxial layer and on the substrate, a first well coupled to the anode, a second well coupled to the cathode, a third well with light doping concentration formed beside the first well, and a guard ring with heavy doping concentration formed in the first well and beside the third well, and between the third well and the second well is a drift region, a lateral breakdown occurs in the third well, the drift region and the second well when a reverse voltage added on the lateral diode is equal to or higher than a breakdown voltage.

Abstract: An LDMOS device with sinker link. The LDMOS device has a buried layer, a first well region and a sinker linking the buried layer and the first well region. The LDMOS device has a trench with its upper portion surrounded by the first well region and its lower portion surrounded by the sinker. The trench is formed so that the sinker can be formed by ion implantation through the trench. The trench is filled with non-conductive material.

Abstract: The present disclosure discloses a lateral transistor having a source region, a drain region, a gate near the source region side and a field dielectric positioned in or atop a portion of a well region between the drain region and the gate. The lateral transistor further includes a non-conductive field plate positioning layer positioned atop a portion of the field dielectric and separated laterally from the gate with a first lateral distance, a lateral conductive field plate positioned atop the non-conductive field plate positioning layer and separated laterally from the gate with a second lateral distance and a vertical trenched field plate contact extending vertically from a top surface of an interlayer dielectric layer through the interlayer dielectric layer to reach and contact with the lateral conductive field plate.

Abstract: A lateral transistor having a well region, a body region, a source region, a drain region, a gate structure and a trenched Schottky barrier structure. The trenched Schottky barrier structure extended vertically from a top surface of the well region through the source region and the body region and penetrated into at least a portion of the well region to form a vertical Schottky contact.

Abstract: A lateral diode with high breakdown voltage capability and a method for forming the lateral diode. The lateral diode has an anode, a cathode, a substrate having a first conductivity type, an epitaxial layer having formed on the substrate, a current region formed in the epitaxial layer and on the substrate, a first well coupled to the anode, a second well coupled to the cathode, a third well with light doping concentration formed beside the first well, and a guard ring with heavy doping concentration formed in the first well and beside the third well, and between the third well and the second well is a drift region, a lateral breakdown occurs in the third well, the drift region and the second well when a reverse voltage added on the lateral diode is equal to or higher than a breakdown voltage.

Abstract: A bipolar junction semiconductor device and associated method of manufacturing, the bipolar junction semiconductor device has a P type substrate, a N type buried layer formed in the substrate, a P? type first epitaxial layer formed on the buried layer, a P? type second epitaxial layer formed on the first epitaxial layer, a PNP BJT unit formed in the first and second epitaxial layers at a first active area, a NPN BJT unit formed in the first and second epitaxial layers at a second active area and a first isolation structure of N type formed in the first and second epitaxial layers at an isolation area. The isolation area is located between the first active area and the second active area, the first isolation structure connected with the buried layer forms an isolation barrier.

Abstract: A bipolar junction semiconductor device and associated method of manufacturing, the bipolar junction semiconductor device has a P type substrate, a N type buried layer formed in the substrate, a P? type first epitaxial layer formed on the buried layer, a P? type second epitaxial layer formed on the first epitaxial layer, a PNP BJT unit formed in the first and second epitaxial layers at a first active area, a NPN BJT unit formed in the first and second epitaxial layers at a second active area and a first isolation structure of N type formed in the first and second epitaxial layers at an isolation area. The isolation area is located between the first active area and the second active area, the first isolation structure connected with the buried layer forms an isolation barrier.

Abstract: A high voltage DMOS device using conventional silicon BCD (Bipolar CMOS DMOS) technology has a P-type buried layer and an N-type buried layer, a first epitaxial layer and a second epitaxial layer. The high voltage DMOS device is characterized in high breakdown voltage, good robustness and low Ron through controlling the thickness of the epitaxial layers, the dose and forming energy of the buried layers. In addition, the high voltage DMOS may further has a shallow drain region to further improve robustness.

Abstract: A JFET having a semiconductor substrate of a first doping type, an epitaxial layer of the first doping type located on the semiconductor substrate, a body region of a second doping type located in the epitaxial layer, a source region of the first doping type located in the epitaxial layer, a gate region of the second doping type located in the body region, and a shielding layer of the second doping type located in the epitaxial layer, wherein the semiconductor substrate is configured as a drain region, the shielding layer is in a conductive path formed between the source region and the drain region.

Abstract: A high side DMOS provides high breakdown voltage with small termination area. The high side DMOS has three parts which may comprise a stair-field plate in the termination part of the poly gate.

Abstract: A high side DMOS provides high breakdown voltage with small termination area. The high side DMOS has three parts which may comprise a stair-field plate in the termination part of the poly gate.

Abstract: A JFET having a semiconductor substrate of a first doping type, an epitaxial layer of the first doping type located on the semiconductor substrate, a body region of a second doping type located in the epitaxial layer, a source region of the first doping type located in the epitaxial layer, a gate region of the second doping type located in the body region, and a shielding layer of the second doping type located in the epitaxial layer, wherein the semiconductor substrate is configured as a drain region, the shielding layer is in a conductive path formed between the source region and the drain region.

Abstract: A semiconductor device having a trench-gate MOSFET and a vertical JFET formed in a semiconductor layer. In the semiconductor device, a gate region of the vertical JFET may be electrically coupled to a source region of the trench-gate MOSFET, and a drain region of the vertical JFET and a drain region of the trench-gate MOSFET may share a common region in the semiconductor layer.