Abstract: An apparatus comprising an interconnect comprising a conductive core; a first conductive layer connected to the conductive core and extending parallel to the conductive core towards a first end of the conductive core; a second conductive layer connected to the conductive core and extending parallel to the conductive core towards a second end of the conductive core; a first non-conductive layer between the conductive core and the first conductive layer; and a second non-conductive layer between the first conductive layer and the second conductive layer.

Abstract: A high volume manufacturing (HVM) test system including a test device defining an opening configured to receive a package under test, the test device including an external access agent (EAA) including: a first leaky surface wave launcher for near field wireless communication, the first leaky surface wave launcher configured to wirelessly provide sideband signals to and wirelessly receive the sideband signals from a silicon package agent physically positioned in a separate package as the EAA; and a first transceiver electrically coupled to the first leaky surface wave launcher, the first transceiver configured to: process the sideband signals received by the first leaky surface wave launcher; and generate the sideband signals for wireless transmission by the first leaky surface wave launcher.

Abstract: A package substrate may include a circuit and a leaky surface wave launcher. The circuit may perform engineering tests and end-user operations using sideband signals. The leaky surface wave launcher may perform near field wireless communication. The leaky surface wave launcher may include a via and a strip line. The via may be electrically coupled to the circuit. The via may provide the sideband signals to and receive the sideband signals from the circuit. The strip line may be electrically coupled to the via. The strip line may be excited by the sideband signals to wirelessly couple the leaky surface wave launcher with an external device. The strip line and the via may be unbalanced such that the strip line generates a leaky wave that propagates at least a portion of the package substrate and an environment proximate the package substrate.

Abstract: Methods and apparatus relating to phase heterogeneous interconnects for crosstalk reduction are described. In one embodiment, an interconnect includes a plurality of links. A first set of links from the plurality of links communicates signals and a second set of links from the plurality of links provides a return path. The interconnect also includes one or more links from the first set of links that include one or more structures with a larger diameter than a minimum diameter of the one or more links. The larger diameter modifies an inductance or capacitance of the one or more links to provide a heterogenous phase delay amongst the plurality of links. Other embodiments are also claimed and disclosed.

Abstract: An apparatus and method for adjusting differential impendence of pins in a socket are described. A socket or test system includes a pin assembly that contains a pin block and pins. The pin block is formed from a material having a first permittivity. The pins include differential pin pairs with a fine pitch and provide electrical contact to an electronic package disposed on the pin block. A volume between each pin of the differential pin pairs or between adjacent pin pairs have a second permittivity that is different than the first permittivity. The volume is filled with air or one or more materials (or air) whose combined permittivity reduces or increases the differential impendence.

Abstract: A package substrate may include a circuit and a leaky surface wave launcher. The circuit may perform engineering tests and end-user operations using sideband signals. The leaky surface wave launcher may perform near field wireless communication. The leaky surface wave launcher may include a via and a strip line. The via may be electrically coupled to the circuit. The via may provide the sideband signals to and receive the sideband signals from the circuit. The strip line may be electrically coupled to the via. The strip line may be excited by the sideband signals to wirelessly couple the leaky surface wave launcher with an external device. The strip line and the via may be unbalanced such that the strip line generates a leaky wave that propagates at least a portion of the package substrate and an environment proximate the package substrate.

Abstract: An apparatus comprising an interconnect comprising a conductive core; a first conductive layer connected to the conductive core and extending parallel to the conductive core towards a first end of the conductive core; a second conductive layer connected to the conductive core and extending parallel to the conductive core towards a second end of the conductive core; a first non-conductive layer between the conductive core and the first conductive layer; and a second non-conductive layer between the first conductive layer and the second conductive layer.

Abstract: In one embodiment, an interconnect apparatus (e.g., an interposer apparatus) includes a plurality of interconnect probes that each include a wave spring structure that includes a plurality of stacked wave spring discs. The wave spring discs may be formed in a sinusoidal wave form shape, or in another wave form shape.

Abstract: An apparatus is described. The apparatus includes an electro-mechanical interface having angled signal interconnects, wherein, the angling of the signal interconnects is to reduce noise coupling between the angled signal interconnects.

Abstract: A system for a three-dimensional (“3D”) printed circuit board (“PCB”) to printed circuit board interface is provided. A first PCB includes first landing pads disposed on one or more edges of the first PCB. The first landing pads electrically couple to conductive pins or second landing pads disposed on a second PCB. The second landing pads may be disposed in a slot in the second PCB. The interface between the first landing pads and the second landing pads may provide various advantages over traditional PCB to PCB interfaces, such as, improved signal integrity, improved power integrity, increased contact density, decreased clock jitter, etc.

Abstract: A system for a three-dimensional (“3D”) printed circuit board (“PCB”) to printed circuit board interface is provided. A first PCB includes first landing pads disposed on one or more edges of the first PCB. The first landing pads electrically couple to conductive pins or second landing pads disposed on a second PCB. The second landing pads may be disposed in a slot in the second PCB. The interface between the first landing pads and the second landing pads may provide various advantages over traditional PCB to PCB interfaces, such as, improved signal integrity, improved power integrity, increased contact density, decreased clock jitter, etc.

Abstract: Electrical interconnects having a non-linear conductive pathway, and related apparatuses and methods, are disclosed herein. In some embodiments, an electrical interconnect may include a non-linear conductive pathway electrically coupling top and bottom conductive portions. In some embodiments, an electrical interconnect may include a non-linear conductive pathway that propagates an electrical signal generating electromagnetic fields with an electrical field orthogonal to the direction of electromagnetic-wave propagation. In some embodiments, an electrical interconnect may include a non-linear conductive pathway portion and a linear conductive pathway portion. Also disclosed are connectors including an electrical interconnect having a non-linear conductive pathway.

Abstract: Embodiments of the present disclosure may relate to a printed circuit board (PCB) that includes a first outer layer and a second outer layer opposite the first outer layer. The PCB may further include a routing layer between the first outer layer and the second outer layer, and an interconnect positioned within the first outer layer and coupled with the routing layer. The interconnect may include a contact within an opening in the first outer layer, wherein the contact is within a plane defined by an outer surface of the first outer layer. The interconnect may further include a plated via directly coupled with the contact and the routing layer. Other embodiments may be described or claimed.