Abstract: A semiconductor light-emitting device includes a substrate, a connection structure disposed on the substrate, a semiconductor light-emitting unit disposed on the connection structure, and first and second electrodes. The connection structure includes an insulating layer formed with a through hole, a first electrically connecting layer disposed on the insulating layer and electrically connected to the first electrode, and a second electrically connecting layer disposed between the substrate and the insulating layer and extending through the through hole to be electrically connected to the second electrode. A projection of the second electrode on the insulating layer covers a portion of the insulating layer.

Abstract: Three-dimensional packaging structure for fan-out of bonding wall of device is provided. A first surface of a device is disposed with bond pads and functional area. The device, except for the first surface, is encapsulated with encapsulation material. A first surface of the encapsulation material horizontally connected to the first surface forms a fan-out surface. A wall structure is disposed on the first surface and extends to the fan-out surface. The wall structure partially covers at least one of the bond pads and comprises first opening corresponding to the at least one of the bond pads. Cover plate is bonded with the wall structure to form cavity corresponding to the functional area and comprises at least one second opening in communication with the first opening. A metal interconnection structure is disposed on surface of the cover plate and is electrically connected to the at least one of the bond pads.

Abstract: An embedded silicon substrate fan-out type 3D packaging structure, comprising: a silicon substrate; and at least one functional chip, wherein the silicon substrate includes at least one groove, the at least one functional chip is embedded in the at least one groove with a pad surface facing upward, the at least one functional chip is bonded with the at least one groove through a polymer; a front surface of the silicon substrate, the pad surface of the at least one functional chip, and at least one gap between the at least one chip and the at least one groove are covered with a polymer material, and the polymer on pads on the at least one functional chip is opened; at least one conductive through hole is formed on the silicon substrate; and the silicon substrate further includes electrical interconnect structures, a first metal re-wiring and a second metal re-wiring.

Abstract: An embedded silicon substrate fan-out type 3D packaging structure, comprising: a silicon substrate; and at least one functional chip, wherein the silicon substrate includes at least one groove, the at least one functional chip is embedded in the at least one groove with a pad surface facing upward, the at least one functional chip is bonded with the at least one groove through a polymer; a front surface of the silicon substrate, the pad surface of the at least one functional chip, and at least one gap between the at least one chip and the at least one groove are covered with a polymer material, and the polymer on pads on the at least one functional chip is opened; at least one conductive through hole is formed on the silicon substrate; and the silicon substrate further includes electrical interconnect structures, a first metal re-wiring and a second metal re-wiring.

Abstract: An embedded silicon substrate fan-out type packaging structure comprises: a silicon substrate having a first surface and a second surface opposite thereto, at least one groove extending towards the second surface being formed on the first surface; at least one chip placed in the groove, a pad surface of the chip being opposite to a bottom of the groove; a second dielectric layer formed on the chip and the first surface; at least one layer of metal wiring connected to pads of the chip, formed on the second dielectric layer; under bump metal layers for planting solder balls, formed on an outermost layer of metal wiring; and solder balls or bumps planted on the under bump metal layers, wherein at least one solder ball or bump and at least one under bump metal layer corresponding thereto are on the first surface of the silicon substrate.

Abstract: A mechanical debonding method and system are provided. A mechanical debonding method, used to debond temporary bonding wafers formed by bonding a device wafer and a carrier wafer by an adhesive, includes: obtaining the height position of the adhesive through a thickness measurement apparatus; moving a cutting apparatus to a position between the device wafer and the carrier wafer based on the height position of the adhesive, then removing the adhesive at the edge of the temporary bonding wafers by the cutting apparatus; removing the carrier wafer from the temporary bonding wafers; cleaning the adhesive left on the surface of the device wafer.

Abstract: A method for avoiding using CMP for eliminating electroplated copper facets and reusing barrier layer in the back end of line (“BEOL”) manufacturing processes. Electropolishing is employed to remove the deposited surface metal, stopping at the barrier layer to form a smooth surface that may be utilized in subsequent steps. The method is suitable for the electropolishing of metal surfaces after formation of filled vias for through-silicon via processes employing metals such as copper, tungsten, aluminum, or alloys thereof. The remaining barrier layer may be reused to fabricate the redistribution layer.

Abstract: A method for avoiding using CMP for eliminating electroplated copper facets and reusing barrier layer in the back end of line (“BEOL”) manufacturing processes. Electropolishing is employed to remove the deposited surface metal, stopping at the barrier layer to form a smooth surface that may be utilized in subsequent steps. The method is suitable for the electropolishing of metal surfaces after formation of filled vias for through-silicon via processes employing metals such as copper, tungsten, aluminum, or alloys thereof. The remaining barrier layer may be reused to fabricate the redistribution layer.

Abstract: A TSV front-top interconnection process is provided. In an embodiment of the present invention, the stress concentration area of a TSV copper pillar is eliminated, which reduces the possibility of generating delamination or cracks between an insulating layer and the substrate due to stress. Meanwhile, the defect of the existing process that the TSV copper pillar may expose after an electroplating and annealing process is re-used to achieve the interconnection between the TSV copper pillar and the metal redistribution layer.

Abstract: A mechanical debonding method and system are provided. A mechanical debonding method, used to debond temporary bonding wafers formed by bonding a device wafer and a carrier wafer by an adhesive, includes: obtaining the height position of the adhesive through a thickness measurement apparatus; moving a cutting apparatus to a position between the device wafer and the carrier wafer based on the height position of the adhesive, then removing the adhesive at the edge of the temporary bonding wafers by the cutting apparatus; removing the carrier wafer from the temporary bonding wafers; cleaning the adhesive left on the surface of the device wafer.

Abstract: A guide wire arrangement, a strip arrangement, a method of forming a guide wire arrangement, and a method of forming a strip arrangement are provided. The guide wire arrangement includes a strip; a sensor being disposed on a first portion of the strip; a chip being disposed next to the sensor on a second portion of the strip, wherein the second portion of the strip is next to the first portion of the strip; wherein the strip is folded at a folding point between the first portion of the strip and the second portion of the strip such that the first portion of the strip and the second portion of the strip form a stack of strip portions.

Abstract: According to embodiments of the present invention, a micro-sensory tip for use in blood vessels is provided. The micro-sensory tip includes: a force transmission element; at least three force detecting sensors coupled to the force transmission element, each of the at least three force detecting sensors responsive to force applied on the force transmission element, wherein each of the at least three force detecting sensors produces an output representing at least one force component of a three-dimensional Cartesian co-ordinate system, of the force experienced by the force transmission element, such that the outputs of the at least three force detecting sensors can cover the space of the three-dimensional Cartesian co-ordinate system; and an active element arrangement coupled to the at least three force detecting sensors, the active element arrangement configured to process the output from the at least three force detecting sensors.

Abstract: According to embodiments of the present invention, an implantable device for detecting variation in fluid flow rate is provided. The implantable device includes: a substrate having an active element arrangement; a sensor arrangement having a first portion that is mechanically secured and a second portion that is freely deflectable, the sensor arrangement in electrical communication with the active element arrangement, wherein the active element arrangement is configured to detect changes in deformation of the sensor arrangement and produce an output in response to the detected changes; and at least one inductive element mechanically coupled to the substrate and in electrical communication with the active element arrangement, wherein the inductive element is adapted to power the active element arrangement through inductive coupling to an excitation source, and wherein the inductive element is adapted to transmit the output associated with the detected changes in the sensor.