Patents by Inventor Dar-Chang Juang

Dar-Chang Juang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160095242
    Abstract: The present invention provides an electronic device with dust protecting function and a method for fabricating the electronic device with dust protecting function. The electronic device comprises: a chamber structure and a first electronic element. The chamber structure comprises: a substrate; and a cap. The cap is connected to the substrate, and has a hole and a protruding part, wherein the protruding part protrudes toward inside of the chamber structure. The first electronic element is disposed in the chamber structure, wherein the protruding part is a block between the first electronic element and the hole of the cap.
    Type: Application
    Filed: September 8, 2015
    Publication date: March 31, 2016
    Inventor: Dar-Chang Juang
  • Patent number: 7199575
    Abstract: A TFT-LCD source driver with a built-in test circuit includes N driving units and P test units. Each driving unit receives digital data and generates an analog output signal according to the digital data. Each test unit receives the analog output signals, selects one of them as a test signal according to a select signal, and compares the test signal with a high reference voltage and a low reference voltage to output an indication signal. The indication signal is set to indicate an abnormal state as the voltage of the test signal is higher than the high reference voltage or lower than the low reference voltage.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: April 3, 2007
    Assignee: Sunplus Technology Co., Ltd.
    Inventors: Lin-Chien Chen, Dar-Chang Juang
  • Publication number: 20070018939
    Abstract: The invention relates to a source driver circuit and method for a LCD device. The source driver circuit includes a plurality of source drivers. Each source driver includes two data buffers, two digital-to-analog converters, two amplifiers, a switch module and two black insertion units. The invention uses the black insertion units to directly provide black insertion voltages required in a black insertion step without use of digital-to-analog converters and amplifiers, thereby achieving higher the driving speed of the source driver circuit and lower power consumption of the amplifiers.
    Type: Application
    Filed: October 6, 2005
    Publication date: January 25, 2007
    Inventors: Lin-Chien Chen, Dar-Chang Juang
  • Publication number: 20060022930
    Abstract: A TFT-LCD source driver with a built-in test circuit includes N driving units and P test units. Each driving unit receives digital data and generates an analog output signal according to the digital data. Each test unit receives the analog output signals, selects one of them as a test signal according to a select signal, and compares the test signal with a high reference voltage and a low reference voltage to output an indication signal. The indication signal is set to indicate an abnormal state as the voltage of the test signal is higher than the high reference voltage or lower than the low reference voltage.
    Type: Application
    Filed: April 26, 2005
    Publication date: February 2, 2006
    Inventors: Lin-Chien Chen, Dar-Chang Juang
  • Patent number: 6731170
    Abstract: A source drive amplifier has a first input circuit controlled by a polarity switching signal for being switched into an NMOS differential amplifying circuit or a bias circuit, and a second input circuit controlled by a polarity switching signal for being switched into a bias circuit or a PMOS differential amplifying circuit. The output of the first input circuit switched into an NMOS differential amplifying circuit drives the PMOS transistor of an output transistor pair for being used as a source out amplifying output stage, and a current provided by the NMOS transistor is used as a bias. The output of the second output circuit switched into a PMOS differential amplifying circuit drives the NMOS transistor of the output transistor pair for being used as a sink in amplifying output stage, and a current provided by the PMOS transistor is used as a bias.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: May 4, 2004
    Assignee: Sunplus Technology Co., Ltd.
    Inventor: Dar-Chang Juang
  • Patent number: 6563295
    Abstract: A low temperature coefficient reference current generator has a bandgap reference voltage generator for providing a low temperature coefficient bandgap reference voltage and a positive temperature coefficient current. The low temperature coefficient reference current generator utilizes the low temperature coefficient bandgap reference voltage to drive a positive temperature coefficient resistor disposed in an IC, so as to produce a negative temperature coefficient current. The positive temperature coefficient current and the negative temperature coefficient current are adjusted and combined to produce a low temperature coefficient reference current.
    Type: Grant
    Filed: January 18, 2001
    Date of Patent: May 13, 2003
    Assignee: Sunplus Technology Co., Ltd.
    Inventor: Dar-Chang Juang
  • Patent number: 6538645
    Abstract: A computer input system utilizing a camera to sense a point source includes a movable light emitting device, which is operated by the user to move and emit at least two lights of different colors. The computer input system further has a camera for capturing the light emitted by the movable light emitting device and transforming a captured light trace produced by the movable light emitting device to XY coordinate data, so as to perform a pointing input operation.
    Type: Grant
    Filed: October 26, 2000
    Date of Patent: March 25, 2003
    Assignee: Sunplus Technology Co., Ltd.
    Inventors: Dar-Chang Juang, Pao-Chyuan Chen
  • Publication number: 20030052854
    Abstract: A source drive amplifier has a first input circuit controlled by a polarity switching signal for being switched into an NMOS differential amplifying circuit or a bias circuit, and a second input circuit controlled by a polarity switching signal for being switched into a bias circuit or a PMOS differential amplifying circuit. The output of the first input circuit switched into an NMOS differential amplifying circuit drives the PMOS transistor of an output transistor pair for being used as a source out amplifying output stage, and a current provided by the NMOS transistor is used as a bias. The output of the second output circuit switched into a PMOS differential amplifying circuit drives the NMOS transistor of the output transistor pair for being used as a sink in amplifying output stage, and a current provided by the PMOS transistor is used as a bias.
    Type: Application
    Filed: June 28, 2001
    Publication date: March 20, 2003
    Inventor: Dar-Chang Juang
  • Publication number: 20020093324
    Abstract: A low temperature coefficient reference current generator has a bandgap reference voltage generator for providing a low temperature coefficient bandgap reference voltage and a positive temperature coefficient current. The low temperature coefficient reference current generator utilizes the low temperature coefficient bandgap reference voltage to drive a positive temperature coefficient resistor disposed in an IC, so as to produce a negative temperature coefficient current. The positive temperature coefficient current and the negative temperature coefficient current are adjusted and combined to produce a low temperature coefficient reference current.
    Type: Application
    Filed: January 18, 2001
    Publication date: July 18, 2002
    Inventor: Dar-Chang Juang
  • Patent number: 6388477
    Abstract: A switchable voltage follower and a bridge driver that utilizes the voltage follower. The voltage follower has an output transistor pair, three switching devices and an operational amplifier. Each of the switching devices is controlled by a polarity terminal for switching the circuit to be a pull-up voltage follower or a pull-down voltage follower. The bridge driver is formed by two switchable voltage followers to provide a bridge push-pull driving capability by driving the two switchable voltage followers alternately.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: May 14, 2002
    Assignee: Sunplus Technology Col, Ltd.
    Inventor: Dar-Chang Juang
  • Patent number: 6384685
    Abstract: A CMOS class AB amplifier has an adaptive level shift circuit, a compensated capacitor, and an output transistor pair. The adaptive level shift circuit includes a current mirror circuit, a diode transistor, a switch transistor, and a current source transistor. The diode transistor is utilized as a bias for driving the switch transistor so as to provide a relatively low linear resistor for being used as a feedback. Therefore, the Q (quality factor) value of the gyration inductance can be effectively reduced and the occurrence of the peak gain can be suppressed effectively, so as to maintain a desired gain margin.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: May 7, 2002
    Assignee: Sunplus Technology Co., Ltd.
    Inventor: Dar-Chang Juang
  • Patent number: 6366116
    Abstract: There is disclosed a programmable driving circuit for being applied in an organic light emitting diode display panel. The driving circuit has a plurality of driver cells, each comprising a switch transistor, a current output transistor, a discharge transistor, and a plurality of multiplexers each for selecting the row driving inputs, column driving inputs, and required bias outputs. By controlling the control terminals of the multiplexers for performing switching controls, the driving circuit is programmed.
    Type: Grant
    Filed: January 18, 2001
    Date of Patent: April 2, 2002
    Assignee: Sunplus Technology Co., Ltd.
    Inventor: Dar-Chang Juang
  • Patent number: 6359309
    Abstract: A MOSFET and IGBT are described that exhibit high breakdown voltage together with low on-resistance. This is achieved by providing an N type shunt that extends from the N+ drain (for power MOSFETs) or P+ emitter (for IGBTs), through the N− region to a short distance below the gate oxide. To manufacture such a shunt, an epi wafer with N−epitaxy is first provided on top of an N+ (for power MOSFET) or P+ (for IGBT) layer. Through a suitable mask (contact or freestanding) on the top surface, the wafer is then subjected to bombardment by protons or deuterons. Because of ion transmutation doping, a region of N type material forms wherever the surface is not masked. By controlling the energies of the ions, this region is caused to extend below the wafer's surface so as to just contact the N+ or P+ layer or even to go through it.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: March 19, 2002
    Assignee: Industrial Technology Research Institute
    Inventors: Chungpin Liao, Dar-Chang Juang
  • Patent number: 6333603
    Abstract: An organic light emission display module is formed by an organic light emission device panel and a driving circuit board. In manufacturing the organic light emission device panel, electrodes are extended to the edges of the panel. The bonding pads are produced by forming aluminum films. The driving circuit board is made of thin printed circuit board, and bonding pads are manufactured at the edges of the printed circuit board, which are corresponding to the bonding pads of the organic light emission device panel, respectively. The driving circuit board is adhered to the organic light emission device panel, and the each bonding pad of the organic light emission device panel is connected to a respective bonding pad of the driving circuit board. Epoxy resin is filled into the bonding area and gaps between the printed circuit board and the organic light emission device panel.
    Type: Grant
    Filed: June 19, 2000
    Date of Patent: December 25, 2001
    Assignee: Sunplus Technology Co., Ltd.
    Inventors: Dar-Chang Juang, Kun-Wei Lin
  • Patent number: 6323631
    Abstract: A constant current driver with auto-clamped pre-charge function includes a reference bias generator and a plurality of constant current driver cells, each being connected to the reference bias generator to form a respective current mirror. Each constant current driver cell has a switch transistor, a current output transistor and a pre-charge transistor. When a constant current is outputted from the current output transistor for driving an organic light emitting diode, the pre-charge transistor is turned on to provide a drain to source current as an additional large current for rapidly pre-charging the organic light emitting diode until the gate to source voltage of the pre-charge transistor is smaller than the threshold voltage.
    Type: Grant
    Filed: January 18, 2001
    Date of Patent: November 27, 2001
    Assignee: Sunplus Technology Co., Ltd.
    Inventor: Dar-Chang Juang
  • Patent number: 6190970
    Abstract: A MOSFET and IGBT are described that exhibit high breakdown voltage together with low on-resistance. This is achieved by providing an N type shunt that extends from the N+ drain (for power MOSFETs) or P+ emitter (for IGBTs), through the N− region to a short distance below the gate oxide. To manufacture such a shunt, an epi wafer with N− epitaxy is first provided on top of an N+ (for power MOSFET) or P+ (for IGBT) layer. Through a suitable mask (contact or freestanding) on the top surface, the wafer is then subjected to bombardment by protons or deuterons. Because of ion transmutation doping, a region of N type material forms wherever the surface is not masked. By controlling the energies of the ions, this region is caused to extend below the wafer's surface so as to just contact the N+ or P+ layer or even to go through it.
    Type: Grant
    Filed: January 4, 1999
    Date of Patent: February 20, 2001
    Assignee: Industrial Technology Research Institute
    Inventors: Chungpin Liao, Dar-Chang Juang
  • Patent number: 6097256
    Abstract: A CMOS (complementary metal-oxide semiconductor) high-frequency ring oscillator is provided for generating an output frequency in response to a control voltage in a wide bandwidth. The ring oscillator is of the type including a plurality of cascaded delay circuits, such as CMOS CSL (common-sense logic) inverters. The ring oscillator is characterized by the additional incorporation of each of the CMOS CSL inverters with either a positive-feedback gate structure or a positive-feedback drain structure so as to improve the output-to-output characteristics of the ring oscillator. More specifically, the ring oscillator is still operable to output an oscillating signal even though the control voltage is reduced to below a certain level, at which point the gain is still larger than 1. The ring oscillator is therefore more advantageous than the prior art both in gain and output-to-output characteristics and is operable over a wide variety of output frequencies, particularly in the low-frequency regions.
    Type: Grant
    Filed: March 11, 1999
    Date of Patent: August 1, 2000
    Assignee: Industrial Technology Research Institute
    Inventors: Dar-Chang Juang, De-Sheng Chen
  • Patent number: 5917378
    Abstract: A rail-to-rail type of operational amplifier is provided, which has a low offset voltage and improved bandwidth, slew rate, and phase margin. This operational amplifier includes two level-shifting input circuits for receiving two input voltages. The input voltages are further divided into four subvoltages which are then processed by a pair of differential amplifiers. The output differential currents from the differential amplifiers are further processed respectively by two current-summing circuits. The potential difference between the outputs of these two current-summing circuits is then fed to a bias circuit which, in response to the input potential difference, generates a floating bias. An output circuit takes the floating bias as input to thereby generate an output voltage which is regarded as the output of the operational amplifier.
    Type: Grant
    Filed: June 27, 1997
    Date of Patent: June 29, 1999
    Assignee: Industrial Technology Research Institute
    Inventor: Dar-Chang Juang
  • Patent number: 5903321
    Abstract: A video image signal processing and recording system provides for operation in a first mode in which real time display of video is provided and in a second mode in which the video image signals are digitized and stored in a memory and being read out and displayed in response to selection of a display mode for the system. In an enhanced mode operation for the system, increasing of the low light intensity value of the displayed real time images or displayed memory images to compensate for low light conditions or for the effects of back lighting. The video image signal processing and recording system is described with reference to an application in a door entry system for a residential building.
    Type: Grant
    Filed: September 24, 1996
    Date of Patent: May 11, 1999
    Assignee: Industrial Technology Research Institute
    Inventors: Pei-Hui Tung, Chen-Pang Kung, Dar-Chang Juang
  • Patent number: 5191606
    Abstract: An electrical telephone speech network is disclosed in which the transmitting and the receiving amplifiers are serially connected so as to reduce the minimum working current of the whole speech network. As a result, a telephone set in the network can operate properly with a much lower line current, and more extension telephones can be connected parallelly with the speech network. Further, a bias switching circuit is matched with the speech network. Thus, in pulse dialing mode, the line voltage drop of the network loop during "make" status is automatically decreased so that a pulse dialing signal received by the exchange can be more accurate. At the same time, in DTMF dialing mode, the voltage drop of the telephone set is automatically increased, for the purpose of providing a larger AC signal dynamic range to enable a telephone set to deliver a large DTMF signal and operate with a lower line current.
    Type: Grant
    Filed: May 8, 1990
    Date of Patent: March 2, 1993
    Assignee: Industrial Technology Research Institute
    Inventor: Dar-Chang Juang