Patents by Inventor Darek Josip Mihocka

Darek Josip Mihocka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230418581
    Abstract: Using a common reference address when processing calls between a native application binary interface (ABI) and a foreign ABI. Based on a caller calling using a reference address, a lookup structure is used to determine whether the reference address is within a memory range storing native code and that the callee is native, or a memory range not storing native code and that the callee is foreign. Execution of a callee is initiated based on one of (i) calling the callee using the reference address within an emulator when the caller is native and the callee is foreign; (ii) calling an entry thunk when the caller is foreign and the callee is native; (iii) calling an exit thunk when the caller is native and the callee is foreign; or (iv) directly calling the callee using the reference address when the caller is native and the callee is native.
    Type: Application
    Filed: June 13, 2023
    Publication date: December 28, 2023
    Inventors: Pedro Miguel SEQUEIRA DE JUSTO TEIXEIRA, Darek Josip MIHOCKA, Jon Robert BERRY, Russell Charles HADLEY, James David CLEARY, Clarence Siu Yeen DANG
  • Patent number: 11720335
    Abstract: A hybrid binary executable under both native processes and compatibility (e.g., emulated) processes. When the hybrid binary is loaded by a native process, the process executes a native code stream contained in the binary directly on a processor. When the hybrid binary is loaded by a compatibility process, the process executes an emulation-compatible (EC) code stream directly on a processor. The hybrid binary format supports folding of code between the native code stream and the EC code stream. The hybrid binary comprises a set of memory transformations which are applied to image data obtained from the binary when the hybrid binary executes under the compatibility process.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: August 8, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Pedro Miguel Sequeira De Justo Teixeira, Darek Josip Mihocka, Jon Robert Berry, Russell Charles Hadley, James David Cleary, Clarence Siu Yeen Dang
  • Patent number: 11403100
    Abstract: Using a common reference address when processing calls among a native ABI and a foreign ABI. Based on caller calling using a reference address, a lookup structure is used to determine whether the reference address is within a memory range storing native code (and that the callee is native) or a memory range not storing native code (and that the callee is foreign). Execution of the callee is initiated based on one of (i) when the caller is native and when the callee is foreign, calling the callee using the reference address within an emulator; (ii) when the caller is foreign and the callee is native, calling an entry thunk; (iii) when the caller is native and the callee is foreign, calling an exit thunk; or (iv) when the caller is native and the callee is native, directly calling the callee using the reference address.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: August 2, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Darek Josip Mihocka, Clarence Siu Yeen Dang, Pedro Miguel Sequeira De Justo Teixeira, Pavlo Lebedynskiy, James David Cleary, Jon Robert Berry, YongKang Zhu, Tiansheng Tan
  • Patent number: 11366666
    Abstract: Using a common reference address when processing calls among a native ABI and a foreign ABI. Based on caller calling using a reference address, a lookup structure is used to determine whether the reference address is within a memory range storing native code (and that the callee is native) or a memory range not storing native code (and that the callee is foreign). Execution of the callee is initiated based on one of (i) when the caller is native and when the callee is foreign, calling the callee using the reference address within an emulator; (ii) when the caller is foreign and the callee is native, calling an entry thunk; (iii) when the caller is native and the callee is foreign, calling an exit thunk; or (iv) when the caller is native and the callee is native, directly calling the callee using the reference address.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: June 21, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Darek Josip Mihocka, Clarence Siu Yeen Dang, Pedro Miguel Sequeira De Justo Teixeira, Pavlo Lebedynskiy, James David Cleary, Jon Robert Berry, YongKang Zhu, Tiansheng Tan
  • Publication number: 20220137942
    Abstract: A function is compiled against a first application binary interface (ABI) and a second ABI of a native first instruction set architecture (ISA). The second ABI defines context data not exceeding a size expected by a third ABI of a foreign second ISA, and uses a subset of registers of the first ISA that are mapped to registers of the second ISA. Use of the subset of registers by the second ABI results in some functions being foldable when compiled using both the first and second ABIs. First and second compiled versions of the function are identified as foldable, or not, based on whether the compiled versions match. Both the first and second compiled versions are emitted into a binary file when they are not foldable, and only one of the first or second compiled versions is emitted into the binary file when they are foldable.
    Type: Application
    Filed: December 14, 2021
    Publication date: May 5, 2022
    Inventors: Pedro Miguel SEQUEIRA DE JUSTO TEIXEIRA, Darek Josip MIHOCKA, Jon Robert BERRY, Russell Charles HADLEY, James David CLEARY, Clarence Siu Yeen DANG
  • Publication number: 20220066780
    Abstract: Using a common reference address when processing calls among a native ABI and a foreign ABI. Based on caller calling using a reference address, a lookup structure is used to determine whether the reference address is within a memory range storing native code (and that the callee is native) or a memory range not storing native code (and that the callee is foreign). Execution of the callee is initiated based on one of (i) when the caller is native and when the callee is foreign, calling the callee using the reference address within an emulator; (ii) when the caller is foreign and the callee is native, calling an entry thunk; (iii) when the caller is native and the callee is foreign, calling an exit thunk; or (iv) when the caller is native and the callee is native, directly calling the callee using the reference address.
    Type: Application
    Filed: August 31, 2020
    Publication date: March 3, 2022
    Inventors: Darek Josip MIHOCKA, Clarence Siu Yeen DANG, Pedro Miguel SEQUEIRA DE JUSTO TEIXEIRA, Pavlo LEBEDYNSKIY, James David CLEARY, Jon Robert BERRY, YongKang ZHU, Tiansheng TAN
  • Patent number: 11231918
    Abstract: A function is compiled against a first application binary interface (ABI) and a second ABI of a native first instruction set architecture (ISA). The second ABI defines context data not exceeding a size expected by a third ABI of a foreign second ISA, and uses a subset of registers of the first ISA that are mapped to registers of the second ISA. Use of the subset of registers by the second ABI results in some functions being foldable when compiled using both the first and second ABIs. First and second compiled versions of the function are identified as foldable, or not, based on whether the compiled versions match. Both the first and second compiled versions are emitted into a binary file when they are not foldable, and only one of the first or second compiled versions is emitted into the binary file when they are foldable.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: January 25, 2022
    Assignee: MICROSOFT TECHNOLOGLY LICENSING, LLC
    Inventors: Pedro Miguel Sequeira De Justo Teixeira, Darek Josip Mihocka, Jon Robert Berry, Russell Charles Hadley, James David Cleary, Clarence Siu Yeen Dang
  • Patent number: 11042422
    Abstract: A hybrid binary executable under both native processes and compatibility (e.g., emulated) processes. When the hybrid binary is loaded by a native process, the process executes a native code stream contained in the binary directly on a processor. When the hybrid binary is loaded by a compatibility process, the process executes an emulation-compatible (EC) code stream directly on a processor. When executing in a compatibility process, the EC code stream can interact with a foreign code stream that executes in an emulator. The foreign code stream can be included in the hybrid binary itself, or can be external to the hybrid binary. The hybrid binary format supports folding of code between the native code stream and the EC code stream. The hybrid binary comprises a set of memory transformations which are applied to image data obtained from the binary when the hybrid binary executes under the compatibility process.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: June 22, 2021
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Pavlo Lebedynskiy, Pedro Miguel Sequeira De Justo Teixeira, Darek Josip Mihocka, Jon Robert Berry, Clarence Siu Yeen Dang, Tiansheng Tan, James David Cleary, Yongkang Zhu, Theodore Maxwell Thomas, Ben Niu, Russell Charles Hadley
  • Patent number: 10481999
    Abstract: Techniques for processing recorded program data are described. In implementations, a trace module in a computing device processes instructions of a recorded program and generates a trace file for program optimization. In implementations, the trace module records a subset of a received program for inclusion in the trace file. The computing device can also or instead be implemented to gather and initiate analysis of application data proactively and without user initiation.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: November 19, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jordi Mola, Juan Carlos Arevalo Baeza, Darek Josip Mihocka
  • Patent number: 10261785
    Abstract: In aspects of arithmetic lazy flags representation for emulation, a host processor system receives application instructions that are designed for execution by a guest processor system that is different than a processor architecture of the host processor system. A host emulator receives an application instruction that includes an arithmetic operation, determines a result value of the arithmetic operation that is performed on integer values, and determines a first state variable and a second state variable. The host emulator also determines whether a subsequent application instruction will need a derivation of a subset of arithmetic flags based in part on a third state variable. The host emulator can then determine that the subsequent application instruction does not need the derivation of the subset of arithmetic flags, and perform the subsequent application instruction without a determination of the third state variable, thereby reducing processor clock cycles to emulate the application instructions.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: April 16, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Darek Josip Mihocka
  • Patent number: 10198341
    Abstract: Embodiments herein are directed to parallel replay of code execution. An embodiment parses trace data comprising a plurality of trace data streams that each represents execution of a corresponding one of a plurality of executable entities, and identifies a plurality of trace sections that each represents one or more events executed by one of the executable entities over a period of time. The embodiment defines an ordering among the trace sections, identifies a point of interest in at least one of the executable entities, and identifies a subset of the trace sections that, when replayed linearly according to the ordering, would encounter the point of interest. The embodiment queues the subset of trace sections in an execution pool for replay by one or more processors. Then, based on the trace data, the embodiment uses the processor(s) to replay two or more of the subset of trace sections in parallel.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: February 5, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jordi Mola, Juan Carlos Arevalo Baeza, Darek Josip Mihocka, Ivette Carreras
  • Publication number: 20180246719
    Abstract: In aspects of arithmetic lazy flags representation for emulation, a host processor system receives application instructions that are designed for execution by a guest processor system that is different than a processor architecture of the host processor system. A host emulator receives an application instruction that includes an arithmetic operation, determines a result value of the arithmetic operation that is performed on integer values, and determines a first state variable and a second state variable. The host emulator also determines whether a subsequent application instruction will need a derivation of a subset of arithmetic flags based in part on a third state variable. The host emulator can then determine that the subsequent application instruction does not need the derivation of the subset of arithmetic flags, and perform the subsequent application instruction without a determination of the third state variable, thereby reducing processor clock cycles to emulate the application instructions.
    Type: Application
    Filed: February 28, 2017
    Publication date: August 30, 2018
    Applicant: Microsoft Technology Licensing, LLC
    Inventor: Darek Josip Mihocka
  • Publication number: 20180173611
    Abstract: Embodiments herein are directed to parallel replay of code execution. An embodiment parses trace data comprising a plurality of trace data streams that each represents execution of a corresponding one of a plurality of executable entities, and identifies a plurality of trace sections that each represents one or more events executed by one of the executable entities over a period of time. The embodiment defines an ordering among the trace sections, identifies a point of interest in at least one of the executable entities, and identifies a subset of the trace sections that, when replayed linearly according to the ordering, would encounter the point of interest. The embodiment queues the subset of trace sections in an execution pool for replay by one or more processors. Then, based on the trace data, the embodiment uses the processor(s) to replay two or more of the subset of trace sections in parallel.
    Type: Application
    Filed: December 21, 2016
    Publication date: June 21, 2018
    Inventors: Jordi Mola, Juan Carlos Arevalo Baeza, Darek Josip Mihocka, Ivette Carreras
  • Publication number: 20180157576
    Abstract: Techniques for processing recorded program data are described. In implementations, a trace module in a computing device processes instructions of a recorded program and generates a trace file for program optimization. In implementations, the trace module records a subset of a received program for inclusion in the trace file. The computing device can also or instead be implemented to gather and initiate analysis of application data proactively and without user initiation.
    Type: Application
    Filed: December 5, 2016
    Publication date: June 7, 2018
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Jordi Mola, Juan Carlos Arevalo Baeza, Darek Josip Mihocka
  • Patent number: 9934126
    Abstract: Augmenting a trace with at least one reverse lookup data structure during indexing of the trace. A method includes receiving trace data observed during execution of executable entit(ies), and replaying a plurality of different sections of the trace data. The replay includes, for each trace section, executing a plurality of code instructions of the executable entit(ies) based on the section's portion of the trace data, and recording attribute(s) observed during the execution of the code instructions along with an identity of the trace section. At least one reverse lookup data structure is created. It associates each of at least a subset of the attributes observed during the replay of the plurality of trace sections with the identity of each trace section in which it was observed. This reverse lookup data structure is stored as part of one or more trace data streams.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: April 3, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jordi Mola, Juan Carlos Arevalo Baeza, Darek Josip Mihocka