Abstract: The present invention is broadly directed to a integrated circuit component with a scalable architecture. In one embodiment, an integrated circuit component is provided comprising logic capable of being configured to interface with a first portion of a system bus, and logic capable of being configured to interface with a companion integrated circuit and to receive information that is communicated from the companion integrated circuit, which information was communicated to the companion integrated circuit via a second portion of the system bus.

Abstract: Embodiments directed to novel systems and method for cache management in a distributed system are described. In one embodiment, a system comprises a plurality of processing nodes, each processing node comprising a functional unit and has a local memory directly coupled therewith. Each processing node, of the plurality of processing nodes, also comprises a cache controller and an associated cache memory. Finally, each processing node of the plurality of processing nodes comprises logic for writing requested data in the associated cache memory if the request for data originated from a functional unit of another node (or for reading requested data from the associated cache memory, if the request for data originated form a functional unit of another node).

Abstract: A system is described that is broadly directed to a system of integrated circuit components. The system comprises a plurality of nodes that are interconnected by communication links. A random access memory (RAM) is connected to each node. At least one functional unit is integrated into each node, and each functional unit is configured to carry out a predetermined processing function. Finally, each RAM includes a coherency mechanism configured to permit only read access to the RAM by other nodes, the coherency mechanism further configured to permit write access to the RAM only by functional units that are local to the node.

Abstract: An error correction code method comprises examining a validator of one of a plurality of data in a data stream at a first processing stage and directing the one of the plurality of data through at least one subsequent processing stage to a corrected output if the validator indicates an error. The method also includes directing the one of the plurality of data to the corrected output if the validator does not indicate an error.

Abstract: A system and method communicate information from a single-threaded application over multiple I/O busses to a computing subsystem for processing. In accordance with one embodiment, a method is provided that partitions state-sequenced information for communication to a computer subsystem, communicates the partitioned information to the subsystem over a plurality of input/output busses, and separately processes the information received over each of the plurality of input/output busses, without first se-sequencing the information.

Abstract: A system and method are provided for routing information in a multi-node network. In one embodiment of a multi-node network comprising a plurality of distributed switching nodes, a method is implemented in at least one of the plurality of nodes for routing information entering the node over a first channel to one of a plurality of other channels. The method comprises obtaining priority information for the information, ascertaining a remaining communication length for the information for each of the plurality of other channels, determining a current demand for each of the plurality of other channels; and routing the information entering at the first channel to one of the other channels based upon an evaluation that considers a combination of the obtained priority information, the ascertained communication length for each of the plurality of other channels, and the current demand for each of the plurality of other channels.

Abstract: A method for allocating buffer capacity includes determining at least one characteristic of a first input/output (I/O) device that is coupled to a memory device interface, the memory device interface being configured to enable data transfers between the I/O device and a memory device, and buffering data corresponding to the first I/O device in a first portion of a buffer of the memory device interface, a size of the first portion being responsive to the at least one characteristic of the first I/O device.

Abstract: The present invention is broadly directed to a integrated circuit component with a scalable architecture. In one embodiment, an integrated circuit component is provided comprising logic capable of being configured to interface with a first portion of a system bus, and logic capable of being configured to interface with a companion integrated circuit and to receive information that is communicated from the companion integrated circuit, which information was communicated to the companion integrated circuit via a second portion of the system bus.