Patents by Inventor Daren Allee

Daren Allee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10338616
    Abstract: A reference circuit constituted of: a voltage/current bias circuitry; a first transistor coupled between a common voltage and an first bias circuitry output; a second transistor coupled between the common voltage and a second bias circuitry output; a third transistor coupled between the common voltage and an output providing a temperature and supply invariant current; a resistor coupled between the second transistor and the second output of the bias circuitry; and an output providing a temperature and supply invariant voltage coupled between the resistor and the second transistor, the voltage output terminal further coupled to a gate of the third transistor, wherein the bias circuitry is arranged, in cooperation with the first transistor, to generate a first current at the first output thereof, and, in cooperation with the second transistor, to generate a second current at the second output thereof, the current magnitudes exhibiting a ratio of a predetermined value.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: July 2, 2019
    Assignee: Microsemi Semiconductor (U.S.) Inc.
    Inventor: Daren Allee
  • Publication number: 20190138040
    Abstract: A reference circuit constituted of: a voltage/current bias circuitry; a first transistor coupled between a common voltage and an first bias circuitry output; a second transistor coupled between the common voltage and a second bias circuitry output; a third transistor coupled between the common voltage and an output providing a temperature and supply invariant current; a resistor coupled between the second transistor and the second output of the bias circuitry; and an output providing a temperature and supply invariant voltage coupled between the resistor and the second transistor, the voltage output terminal further coupled to a gate of the third transistor, wherein the bias circuitry is arranged, in cooperation with the first transistor, to generate a first current at the first output thereof, and, in cooperation with the second transistor, to generate a second current at the second output thereof, the current magnitudes exhibiting a ratio of a predetermined value.
    Type: Application
    Filed: October 25, 2018
    Publication date: May 9, 2019
    Applicant: Microsemi Semiconductor (U.S.) Inc.
    Inventor: Daren ALLEE
  • Publication number: 20010052799
    Abstract: A logic gate includes a low noise current source coupled between a first terminal of a voltage supply and an output terminal. The low noise current source is capable of delivering a preselected voltage signal to the output terminal having a magnitude responsive to a first control signal relatively independent of the magnitude of the voltage on said first terminal of said voltage supply. At least one switching element is coupled between the output terminal and a second terminal of the voltage supply. The switching element is capable of coupling the output terminal to the second terminal of the voltage supply in response to receiving a second control signal.
    Type: Application
    Filed: September 20, 1999
    Publication date: December 20, 2001
    Inventor: DAREN ALLEE
  • Patent number: 6236280
    Abstract: A voltage controlled oscillator has first and second complementary output terminals. A first edge delay circuit has an input terminal, an output terminal, and a control input terminal. The input terminal is coupled to the first complementary output terminal. A first comparator has a first, second and third input terminal, an output terminal, and a control input terminal. The first input terminal is coupled to the output terminal of the first edge delay circuit. The second input terminal is coupled to the first complementary output terminal. The first comparator output terminal is coupled to the second complementary output terminal. A second edge delay circuit has an input terminal, an output terminal, and a control input terminal. The input terminal is coupled to the second complementary output terminal. A second comparator has a first, second and third input terminal, an output terminal, and a control input terminal. The first input terminal is coupled to the output terminal of the second edge delay circuit.
    Type: Grant
    Filed: September 20, 1999
    Date of Patent: May 22, 2001
    Assignee: Advanced Micro Devices Inc.
    Inventor: Daren Allee
  • Patent number: 6208125
    Abstract: A low noise current source is provided. A resistor and a transistor are serially coupled with the resistor and adapted to be coupled between a first terminal of a voltage supply and an output terminal. The transistor is capable of delivering a preselected voltage signal to the output terminal having a magnitude responsive to a first control signal relatively independent of the magnitude of the voltage on the first terminal of the voltage supply.
    Type: Grant
    Filed: September 20, 1999
    Date of Patent: March 27, 2001
    Assignee: Lergity, Inc.
    Inventor: Daren Allee
  • Patent number: 5818293
    Abstract: A phase-locked-loop circuit including a prescaler which divides the frequency of an output signal to thereby generate a frequency-divided signal which is provided as a feedback signal to a phase detector of the phase-locked-loop circuit. The prescaler includes a plurality of analog flip-flop circuits serially connected in a chain, with one or more outputs of latter analog flip-flop stages in the chain being fed back to one or more inputs of the first analog flip-flop. Embedded logic is integrated with the differential input pair of the first analog flip-flop to conditionally control the output of the first analog flip-flop based upon the feedback signals from the latter flip-flop stages. The analog flip-flop with embedded logic includes a master section for setting a state of a differential set up signal in response to an occurrence of a first phase of a clock signal.
    Type: Grant
    Filed: February 26, 1997
    Date of Patent: October 6, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Geoffrey E. Brehmer, Daren Allee