Abstract: A system and method are disclosed for identifying monitoring and evaluating hazardous or potentially hazardous conditions. The system may be worn by safety personnel to detect equipment conditions such as low power supply, environmental conditions such as ambient temperature and/or physiological conditions such as heart rate of a wearer. The system may further include a control unit having electronics operable to communicate signals associated with equipment, environmental and physiological conditions.

Abstract: A system and method are disclosed for identifying monitoring and evaluating hazardous or potentially hazardous conditions. The system may be worn by safety personnel to detect equipment conditions such as low power supply, environmental conditions such as ambient temperature and/or physiological conditions such as heart rate of a wearer. The system further includes a control unit having electronics operable to communicate signals associated with equipment, environmental and physiological conditions.

Abstract: A system and method are disclosed for identifying monitoring and evaluating hazardous or potentially hazardous conditions. The system may be worn by safety personnel to detect equipment conditions such as low power supply, environmental conditions such as ambient temperature and/or physiological conditions such as heart rate of a wearer. The system further includes a control unit having electronics operable to communicate signals associated with equipment, environmental and physiological conditions.

Abstract: A digital computer system having a plurality of working registers in at least one workspace in its main memory and having a workspace pointer register for indicating the location of the workspace also has a workspace cache memory made up of registers corresponding to the working registers in the workspace of the main memory. Computer operations are implemented using the contents of the workspace cache registers whose contents are transmitted to the corresponding working registers in the workspace of the main memory in the event of a context switch. Advantageously, the architecture of this workspace system achieves high speed register-to-register operations and high speed context switching.

Abstract: A coupler pair provides the communication link between two multiprocessors wherein each multiprocessor comprises a plurality of master and slave devices interconnected by a communication bus. The coupler pair provides a communication path between any master device on one of the communication buses and any slave device on the opposite communication bus. More generally a plurality of coupler pairs provides inter-communication within a polysystem comprised of a plurality of multiprocessors.

Abstract: An arithmetic logic unit bit-slice implemented as an integrated circuit is able to perform iterative algorithms such as multiply and divide, using control logic which is also part of the integrated circuit to cause the selected algorithm to be performed. A plurality of the arithmetic logic unit bit-slices may be concatenated to provide the word size desired. The bit-slices are electrically identified as the most significant, least significant, and middle digits, such identification being provided to the control logic so that the control logic is identical on each bit-slice irresepective of its position within a word to enable the control logic to cause performance of the algorithms for any desired word length.