Abstract: A method and structure for determining a listing of host processors on a network to perform a parallel application, including determining a listing of all possible hosts on the network for performing the parallel application, determining for each of the possible hosts a current capacity and a current utilization, calculating for each of the possible hosts a difference between the current capacity and the current utilization, and selecting from the listing of all possible hosts a listing of hosts based on sorting the calculated differences.

Abstract: A method and structure for determining a listing of host processors on a network to perform a parallel application, including determining a listing of all possible hosts on the network for performing the parallel application, determining for each of the possible hosts a current capacity and a current utilization, calculating for each of the possible hosts a difference between the current capacity and the current utilization, and selecting from the listing of all possible hosts a listing of hosts based on sorting the calculated differences.

Abstract: A system, method and program product for predicting yield of a VLSI design. A method is providing including the steps of: identifying and grouping sub-circuits contained within an integrated circuit design by type; calculating critical area values for regions within the integrated circuit design; and applying different yield models to critical area values based on the types of the regions used to calculate the critical area values, wherein each yield model is dependent on a type.

Abstract: Disclosed is a method and structure that partitions an integrated circuit design by identifying logical blocks within the integrated circuit design based on size heuristics of logical macros in the design hierarchy. The invention determines whether the number of logical blocks is within a range of desired number of logical blocks and repeats the process of identifying logical blocks for different hierarchical levels of the integrated circuit design until the number of logical blocks is within the range of the desired number of logical blocks. This serves as a guide to partition the chip as opposed to a grid-like partitioning.