Abstract: A method and arrangement are disclosed involving receiving a read-type command at a data storage arrangement, calculating a command span of the received read-type command and performing a look-up command, through use of a processor, for data located in each extent at a condensed logical block address state table for the read-type command, wherein the condensed logical block address state table describes a logical to physical table and at least one of transmitting data and displaying data related to the read-type command found in the condensed logical block address state table.

Abstract: Embodiments of the present disclosure generally relate to managing phys of a data storage target device. In one embodiment, a method of automatically managing phys of a data storage target device by a controller of the data storage device across a link reset includes transmitting a common target phy address for a plurality of target phys during a first link reset, storing the common target phy address in a non-volatile memory of the data storage device, resetting the target phys, and transmitting the stored common target phy address for the plurality of target phys during a second link reset. In another embodiment, a method of automatically managing phys of a data storage target device by a controller of the data storage device includes matching a received host address for a plurality of target phys and configuring the plurality of target phys into a wide port for the plurality of target phys with the matched received host address.

Abstract: A method for control of latency information through logical block addressing is described comprising receiving a computer command, performing a read flow operation on a computer buffer memory based on the computer command; populating at least one metadata frame with data based on logical block address latency information; initiating a serial attached data path transfer for one of transmitting and receiving data to the computer drive and transmitting data to a host based on the second latency.

Abstract: Embodiments of the present disclosure generally relate to managing phys of a data storage target device. In one embodiment, a method of managing phys of a data storage target device includes waiting to receive a host address on a target phy and transmitting a target phy address for the target phy after waiting to receive the host address on the target phy. In another embodiment, a method of managing phys of a data storage target device includes configuring a target port comprising a first target phy and reconfiguring the target port comprising a first target phy and a second target phy.

Abstract: A device having a controller configured to execute a range crawler algorithm residing in firmware or hardware and a data table containing one or more range entries (RE's), where each of the RE's is part of a logical block address (LBA) span associated with a command instruction, and where each LBA span has one or more LBA ranges, and where each LBA range is made of one or more sequential LBA's. The device also includes a collision bitmap configured to store data associated with RE collisions between one or more LBA's and a command dispatcher configured to release selected LBA ranges that are not associated with a RE collision. The range crawler algorithm is configured to search the data table to detect collisions between the RE's.

Abstract: A memory device is provided that includes a memory location configured to store information representing data written using a first encryption/decryption method, a read channel configured to read and decrypt information using a second encryption/decryption method and an apparatus configured to prevent the read channel from reading the memory location using the second encryption/decryption method.

Abstract: A method for control of latency information through logical block addressing is described comprising receiving a computer command, performing a read flow operation on a computer buffer memory based on the computer command; populating at least one metadata frame with data based on logical block address latency information; initiating a serial attached data path transfer for one of transmitting and receiving data to the computer drive and transmitting data to a host based on the second latency.

Abstract: A method and apparatus that provides a solid state drive that analyzes connection performance during I/O operations and is configured to independently modify connection performance based upon user specified input parameters without the need for host computer management.

Abstract: Embodiments of the present disclosure generally relate to managing phys of a data storage target device. In one embodiment, a method of managing phys of a data storage target device includes waiting to receive a host address on a target phy and transmitting a target phy address for the target phy after waiting to receive the host address on the target phy. In another embodiment, a method of managing phys of a data storage target device includes configuring a target port comprising a first target phy and reconfiguring the target port comprising a first target phy and a second target phy.

Abstract: An arrangement is disclosed comprising a memory arrangement configured to store and retrieve data; an interface to allow data to be received and transmitted by the arrangement from a host and a processor configured to dynamically conduct automatic performance tuning for the memory arrangement.

Abstract: A method includes receiving, by a hardware controller of a storage device and from a host device, a command to read data from or write data to a non-volatile memory device of the storage device. The method includes, responsive to receiving the command: initializing, by firmware executing at a processor of the hardware controller, a command to retrieve data from or write data to the non-volatile memory device; determining, by circuit logic of the hardware controller, a time indicative of when the firmware initialized the command; determining, by the circuit logic, a time indicative of when the command terminated; and storing, by the circuit logic and at a latency monitoring cache of the storage device, a timestamp associated with the time indicative of when the command was initialized and a timestamp associated with the time indicative of when the command terminated.

Abstract: A memory device including at least one memory location for storing information representing data written using a first encryption/decryption method, and a read channel using a second encryption/decryption method for reading and decrypting information as written is disclosed. The memory device also includes an apparatus that prevents the reading of the at least one memory location using the second encryption/decryption method, in response to an indication that the at least one memory location was written using the first encryption/decryption method. In another embodiment, a reading of a predefined or custom code is returned in response to an indication of another encryption/decryption method.

Abstract: An arrangement is disclosed comprising a memory arrangement configured to store and retrieve data; an interface to allow data to be received and transmitted by the arrangement from a host and a processor configured to dynamically conduct automatic performance tuning for the memory arrangement.

Abstract: A method and arrangement for providing warnings based upon potential security compromising actions is discussed. Monitoring of system changes, temperature, humidity, power levels and reconfiguration of system components is performed and compared to threshold levels, with warning generated when monitored conditions fall outside of expected bounds.

Abstract: A method for control of latency information through logical block addressing is described comprising receiving a computer command, performing a read flow operation on a computer buffer memory based on the computer command; populating at least one metadata frame with data based on logical block address latency information; initiating a serial attached data path transfer for one of transmitting and receiving data to the computer drive and transmitting data to a host based on the second latency.

Abstract: Embodiments of the present disclosure generally relate to managing phys of a data storage target device. In one embodiment, a method of managing phys of a data storage target device includes waiting to receive a host address on a target phy and transmitting a target phy address for the target phy after waiting to receive the host address on the target phy. In another embodiment, a method of managing phys of a data storage target device includes configuring a target port comprising a first target phy and reconfiguring the target port comprising a first target phy and a second target phy.

Abstract: Embodiments of the present disclosure generally relate to managing phys of a data storage target device. In one embodiment, a method of automatically managing phys of a data storage target device by a controller of the data storage device across a link reset includes transmitting a common target phy address for a plurality of target phys during a first link reset, storing the common target phy address in a non-volatile memory of the data storage device, resetting the target phys, and transmitting the stored common target phy address for the plurality of target phys during a second link reset. In another embodiment, a method of automatically managing phys of a data storage target device by a controller of the data storage device includes matching a received host address for a plurality of target phys and configuring the plurality of target phys into a wide port for the plurality of target phys with the matched received host address.

Abstract: A memory device including at least one memory location for storing information representing data written using a first encryption/decryption method, and a read channel using a second encryption/decryption method for reading and decrypting information as written. The memory device also includes an apparatus that prevents the reading of the at least one memory location using the second encryption/decryption method, in response to an indication that the at least one memory location was written using the first encryption/decryption method. In another embodiment, a reading of all zeroes is returned in response to an indication of another encryption/decryption method.

Abstract: A controller of a storage device is described for handling communications with a host device. In some examples, the storage device includes a wide port comprising a plurality of phys. The wide port is configured to receive, via a first phy of the plurality of phys, a signal. The controller is configured to select, based on a respective power factor associated with each respective phy of the plurality of phys and a respective performance factor associated with each respective phy of the plurality of phys, a second phy of the plurality of phys to utilize for performing an operation associated with the received signal. In such examples, the wide port is further configured to perform, using the second phy, the operation associated with the received signal.

Abstract: A method is described that includes generating, by a controller of a storage device, operating statistics associated with an operating state of the storage device. The method includes receiving, by the controller and from a host device, a non-interrupt command frame that requests transfer of data blocks between the storage device and the host device. The method further includes, in response to receiving the non-interrupt command frame, generating, by the controller, a response frame associated with the non-interrupt command frame, wherein the response frame includes the operating statistics. The method includes transmitting, by the controller and to the host device, the response frame.