Abstract: The inventions herein are directed to an inventive bus keeper and logic circuit for use with an I/O circuit, for example, for use on the receiver side of the I/O buffer circuit. The inventive circuit connects one data line of an IC function to one line of a tri-state bus (one bit of data per bus line or wire). The bus keeper and logic control circuit is maintained in isolation from I/O functional driver and is responsive to a tri-state signal (TS), normally provided by the IC or SOC, or the I/O circuit during normal I/O receiver side operation. The inventive bus keeper and logic circuit selectively enables any of a tri-state state, a pull-up state, pull-down state and bus keep mode state at the driver output pad in the presence of the tri-state enable signal, and is disabled when the I/O bus drive buffer circuit is in drive mode.

Abstract: The inventions herein are directed to an inventive bus keeper and logic circuit for use with an I/O circuit, for example, for use on the receiver side of the I/O buffer circuit. The inventive circuit connects one data line of an IC function to one line of a tri-state bus (one bit of data per bus line or wire). The bus keeper and logic control circuit is maintained in isolation from I/O functional driver and is responsive to a tri-state signal (TS), normally provided by the IC or SOC, or the I/O circuit during normal I/O receiver side operation. The inventive bus keeper and logic circuit selectively enables any of a tri-state state, a pull-up state, pull-down state and bus keep mode state at the driver output pad in the presence of the tri-state enable signal, and is disabled when the I/O bus drive buffer circuit is in drive mode.

Abstract: A driver including boost circuitry for reducing tri-state delay. Boost circuitry includes boost legs (32) and (34) having boost delay chains (38) and (40), respectively. Subcircuits (35) and (39) may include a series of inverters or other devices to delay a tri-state enable signal (EN2) or (EN2BAR) for a predetermined amount of time substantially equivalent to the time it takes for a first signal (A2) to travel from input pin A to PAD. Transient current provides a boost by discharging or charging output nodes (G1) and (G2), respectively. Boost legs (32) and (34) remain on for the length of time it takes for enable signal (EN2) or (EN2BAR) to travel through subcircuits (35) and (39). The boost increases the rate of transition of output nodes (G1) and (G2) thereby reducing the delay of tri-state signal (EN2).