Abstract: Pipeline structure that is arranged to allow 1.5 cycle access time for both data and instruction cache without imposing additional instruction step delays than that imposed by data and instruction cache that have 1 cycle access time. Half cycle pulses are produced to allow execution of various instructions in 0.5 cycles. A bypass signal is generated to allow data from a current load instruction to be available for a second subsequent instruction even though the access time for data cache is 1.5 cycles. Additionally, a branch address is available for a third subsequent instruction even though instruction cache access time is 1.5 cycles. The present invention shows the initiation of an instruction step for each cycle and 1.5 cycle access time for cache memory. The present invention can also be implemented by implementing an instruction every 2 cycles and providing 3 cycle access time for cache memory.

Abstract: Circuit points in an integrated circuit (IC) are monitored at pads normally used to carry information between ports of a normal source on the IC (such as input/output points of a cache control), and a memory unit off the IC. The pads are time-shared between their normal and monitoring functions. Each pad is shared by a port of the normal source (the cache control) and a pair of alternative sources to be monitored. During times when the alternative sources are accessed through a pad, they are connected to it alternately, so that, on a first level, each pad is shared between a normal source and a pair of alternative sources, and, on a second level, each such pad is shared between the two alternative sources when they are being accessed.