Abstract: A microprocessor including a temperature sensor that monitors a temperature of core logic of the microprocessor during operation thereof, and operating point information from which may be determined N operating points at which the microprocessor core may reliably operate at a first temperature. Each of the N operating points has a different combination of operating frequency and voltage. The N operating points comprise a highest operating point, a lowest operating point, and a plurality of operating points intermediate the highest and lowest operating points. The microprocessor also includes a control circuit that transitions operation of the core logic among the N operating points to attempt to keep the operating temperature of the core logic provided by the temperature sensor within a temperature range whose upper bound is the first temperature.

Abstract: A temperature sensor in a microprocessor monitors its operating temperature Operating point data includes a first temperature being the maximum temperature at which the microprocessor will reliably operate at a first frequency and first voltage, the first frequency being the maximum frequency at which the microprocessor will reliably operate at the first temperature and the first voltage. Operating point data also includes a second temperature at which the microprocessor will reliably operate at a second frequency and a second voltage, the second frequency being greater than the first frequency and the second temperature less than the first temperature. A control circuit causes the microprocessor to operate at the second voltage and frequency rather than the first voltage and frequency in response to detecting that while operating at the first voltage and the first frequency the operating temperature dropped below the second temperature.

Abstract: A microprocessor includes core logic that operates according to a core clock signal in order to execute program instructions, clock generation circuitry controllable to generate the core clock signal having one of N different possible frequencies, wherein N is more than two, and a control circuit. The control circuit, in response to a request to operate the core logic at a destination frequency, iteratively controls the clock generation circuitry to generate the core clock signal having a new frequency until the core clock signal frequency is the destination frequency. The new core clock signal frequency on each iteration is one of the N different possible frequencies monotonically closer to the destination frequency. The number of iterations is between zero and N?1 depending upon the destination frequency specified and the core clock signal frequency when the request is received.

Abstract: A microprocessor capable of dynamically reducing its power consumption based on its varying operating temperature includes a temperature sensor that monitors the microprocessor's operating temperature and a control circuit that includes operating point data. The operating point data includes a first voltage at which the microprocessor may reliably operate at a frequency and at a first temperature, and a second voltage at which the microprocessor may reliably operate at the frequency and at a second temperature. The second temperature is less than the first temperature and the second voltage is less than the first voltage. The control circuit causes the microprocessor to operate at the frequency and at the second voltage rather than at the first voltage when the operating temperature drops below the second temperature while operating at the frequency and at the first voltage.

Abstract: A method of dynamically configuring a temperature profile in an integrated circuit (IC). The method includes sensing temperature of the IC, configuring a reduced operating temperature range for the IC, and modulating at least one control mechanism to maintain the temperature of the IC within the reduced operating temperature range.

Abstract: The present invention provides a technique for enabling multiple devices to be interfaced together over a bus that requires dynamic impedance controls. In one embodiment, an apparatus is provided for enabling a multi-device environment on a bus, where the bus requires active termination impedance control. The apparatus includes a first node and multi-processor logic. The first node receives an indication that a corresponding device is at a physical end of the bus. The multi-processor logic is coupled to the first node. The multi-processor logic controls how a second node is driven according to the indication, where the second node is coupled to the bus.

Abstract: A test system including a device under test (DUT) and a tester, where the DUT includes I/O interface logic and a clock circuit. The clock circuit includes a core clock circuit, a pad clock circuit, a test clock circuit, and a select circuit. The core clock circuit generates a core clock signal enabling full speed operation of core circuitry of the IC during test mode. The pad clock circuit generates a preliminary clock signal suitable for normal operation, and the test clock circuit generates a test clock signal suitable for operating the I/O interface logic during the test mode. The select circuit selects, based on the test signal, between the test clock signal and the preliminary clock signal as the pad clock signal. The tester provides the bus clock signal and indicates the test mode to the DUT via the I/O interface logic.

Abstract: An integrated device for sampling data packets asserted sequentially on a system bus, including a clock input for receiving a bus clock signal, a data bus interface for receiving the data packets and for detecting at least one data strobe indicating data validity, and dynamic source synchronized sampling adjust logic. The dynamic source synchronized sampling adjust logic includes sampling logic which selects and latches each data packet in response to the data strobe and which provides latched data packets, and select logic which selects from among the latched data packets based on a read pointer. A method of sampling data packets asserted sequentially on a data bus for one or more bus clock cycles including detecting operative edges of a data strobe, selecting a data packet for each detected operative edge, and latching each selected data packet.

Abstract: A microprocessor including processor logic and sparse write logic. The processor logic asserts address and request signals to provide an address and a request for a cache line memory write transaction. The sparse write logic causes the processor logic to modify a second part of the write request to specify the sparse write command value and to provide the corresponding enable bits. The sparse write-combined memory write transaction may be a quad-pumped cache line write transaction for writing eight quadwords in which each enable bit identifies a corresponding doubleword. A method of performing a sparse write-combined write transaction including providing an address and a request for a memory write transaction, indicating that the memory write transaction is a sparse write-combined write transaction, asserting enable signals for the sparse write-combined write transaction, and providing data for the sparse write-combined write transaction.

Abstract: A microprocessor apparatus is provided, for performing a self-snoop operation. The microprocessor apparatus includes output driver logic and bypass logic. The output driver logic is configured to drive a latched signal out to a bus. The bypass logic is coupled to the latched signal. The bypass logic is configured to provide the latched signal as a snoop result during the self-snoop operation.

Abstract: A microprocessor including a cache memory and bus interface logic. The bus interface logic is interfaced with request signals and data signals and includes a request interface and a response interface. The request interface provides a request via the request signals for a data transaction in which the request specifies a selected burst order. The response interface stores data received via the data signals into the cache memory according to the selected burst order. The request interface may specify the selected burst order by configuring a field of a request packet during a request phase of the data transaction. The selected burst order may selected from any of several different data transaction orderings, including an interleaved order, a linear order, a nibble linear order and a custom order. The microprocessor may further include instruction logic which provides an instruction to the bus interface logic specifying the selected burst order.

Abstract: A microprocessor interface system including a system bus with a bus clock and a data signal group in which multiple devices are coupled to the system bus. Each device is configured to perform a half-width data transaction on the system bus in which a doubleword is transferred for each of four beats during each of four consecutive cycles of the bus clock. The data signal group may include multiple data strobes, such as first and second data strobes for latching first and third doublewords and third and fourth data strobes for latching second and fourth doublewords during each cycle of the bus clock. Each doubleword may be provided on first and second data portions of the data signal group. The first and second data strobes may latch data on the first data portion and the third and fourth data strobes may latch data on the second data portion.

Abstract: A method of performing contiguous write transactions on a processor bus according to an embodiment of the present invention includes detecting, by a bus agent, a request for a write cycle, asserting, by the bus agent, a target ready signal for one clock cycle in response to the write cycle during a first clock cycle of a data transfer phase of a prior write cycle or during a second clock cycle of a data transfer phase of a prior read cycle, asserting, by the bus agent, response signals in a next clock cycle following the clock cycle in which the target ready signal is asserted, asserting, by a processor, a data busy signal for the write cycle in the next clock cycle following the clock cycle in which the response signals are asserted, and asserting, by the processor, data for the write cycle when the data busy signal is asserted.

Abstract: A microprocessor interface system including a system bus with a bus clock and a quad-pumped address signal group, and including multiple devices coupled to the system bus. Each device is configured to perform a quad-pumped transaction on the system bus in which multiple request packets are sequentially transferred via the address signal group during each of multiple phases of one cycle of the bus clock. The devices may include at least one microprocessor and one or more bus agents. In one embodiment, the first address data is multiplexed onto the address signal group during first and second request packets during a first phase of the bus clock cycle, and the second address data is multiplexed onto the address signal group during third and fourth request packets during a second phase of the bus clock cycle.

Abstract: An integrated circuit including a temperature sensor, configurable temperature profile logic, at least one controller, and temperature control logic. The temperature sensor provides an operating temperature value. The configurable temperature profile logic provides a configured operating temperature range. The temperature control logic has a first input receiving the operating temperature value, a second input receiving the configured operating temperature range, and at least one output coupled to each controller. The temperature control logic controls one or more controllers to maintain the operating temperature value within the configured operating temperature range. The IC may include an interface mechanism that enables external configuration of the configurable temperature profile logic, such as a system BIOS interface, an operating system interface and an application program interface.

Abstract: A microprocessor including processor logic and sparse write logic which asserts address signals and request signals to provide an address and a request for a cache line memory write transaction, which provides one of multiple sparse memory write transactions on the request signals and which provides corresponding enable bits on the address signals. Each sparse memory write transaction corresponds with one of multiple granularities of data. For example, if the sparse memory write transaction is a quad-pumped cache line write for eight quadwords, the enable bits may be a selected one of byte, word, doubleword, quadword, doublequadword, etc., enable bits. A method of performing a sparse write transaction including providing an address and a request for a memory write transaction, indicating that the memory write transaction is a selected sparse write transaction, asserting enable signals for the selected sparse write transaction, and providing data for the sparse write transaction.

Abstract: A sense mechanism for data bus inversion including a first memory device and an analog adder. The first memory device stores bits of the bus in a previous bus cycle. The analog adder compares the bits of the bus in the previous bus cycle with bits of the bus in a current bus cycle and provides a data inversion signal indicative of whether more than half of the bits of the bus have changed state. The analog adder operates as a bus state change sense device which rapidly evaluates bus state changes from one bus cycle to the next. The data inversion signal is used for selectively inverting the data bits of the bus and indicating bus inversion according to data bus inversion operation, such as according to X86 microprocessor protocol.

Abstract: A microprocessor temperature control system including a microprocessor with on-chip fan control logic, a fan, and temperature sense logic. The fan control logic receives temperature information and provides a fan control signal to cool the microprocessor. The fan is externally mounted to the microprocessor and has a control input that receives the fan control signal. The temperature sense logic provides the temperature information associated with the microprocessor. The fan control logic may be configured to turn the fan on and off or to control rotational speed of the fan. The temperature sense logic may include at least one temperature sensitive device placed on the die of the microprocessor. In addition or in the alternative, the temperature sense logic is external to the microprocessor for providing the temperature information via an external interface.

Abstract: A power management controller for instantaneous frequency-based microprocessor power management including first and second PLLs, select logic, and source control logic. The first PLL generates a first core source clock signal at a first frequency based on a bus clock signal. The second PLL generates a second core source clock signal at a programmable frequency based on a frequency control signal and the bus clock signal. The select logic selects between the first and second core source clock signals to provide a core clock signal for the microprocessor based on a select signal. The source control logic detects power conditions via at least one power sense signal, provides the frequency control signal according to the power conditions, and provides the select signal. The power management controller enables transition from one power state to another in a single clock cycle, which is significantly faster than conventional power management techniques.

Abstract: A frequency-voltage mechanism for power management including first and second PLLs, select logic, control logic, and voltage control logic. The first PLL generates a first source clock signal at a first frequency based on a bus clock signal. The second PLL generates a second source clock signal at a second frequency based on a first frequency control signal and the bus clock signal. The select logic selects between the first and second source clock signals to provide a core clock signal based on a select signal. The clock control logic detects power conditions via at least one power sense signal, provides the first frequency control signal according to power conditions, and provides the select signal. The voltage control logic adjusts the operating voltage commensurate with frequency of the core clock signal. Power consumption is dynamically adjusted without undue delay while providing significant power efficiency benefits.