Abstract: A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A sidewall spacer (156) is formed against an edge (137) of a layer of bottom electrode/copper diffusion barrier material (136), an edge (151) of a layer of capacitor dielectric material (150) and at least some of an edge (153) of a layer of top electrode material. The sidewall spacer (156) is dielectric or non-conductive and mitigates “shorting” currents that can develop between the plates as a result of copper diffusion. Bottom electrode diffusion barrier material (136) mitigates copper diffusion and/or copper drift, thereby reducing the likelihood of premature device failure.

Abstract: A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A layer of bottom electrode/copper diffusion barrier material (136) is formed (16) within an aperture (128) wherein the capacitor (100) is to be defined. The bottom electrode layer (136) is formed via a directional process so that a horizontal aspect (138) of the layer (136) is formed over a metal (110) at a bottom of the aperture (128) to a thickness (142) that is greater than a thickness (144) of a sidewall aspect (148) of the layer (136) formed upon sidewalls (132) of the aperture (128). Accordingly, the thinner sidewall aspects (148) are removed during an etching act (18) while some of the thicker horizontal aspect (138) remains. A layer of capacitor dielectric material (150) is then conformally formed (20) into the aperture 128 and over the horizontal aspect (138).

Abstract: The present invention provides a method and product-by-method of integrating a bias resistor in circuit with a bottom electrode of a micro-electromechanical switch on a silicon substrate. The resistor and bottom electrode are formed simultaneously by first sequentially depositing a layer of a resistor material (320), a hard mask material (330) and a metal material (340) on a silicon substrate forming a stack. The bottom electrode and resistor lengths are subsequently patterned and etched (350) followed by a second etching (360) process to remove the hard mask and metal materials from the defined resistor length. Finally, in a preferred embodiment, the bottom electrode and resistor structure is encapsulated with a layer of dielectric which is patterned and etched (370) to correspond to the defined bottom electrode and resistor.

Abstract: A rugged polysilicon electrode for a capacitor has high surface area enhancement with a thin layer by high nucleation density plus gas phase doping which also enhances grain shape and oxygen-free dielectric formation.

Abstract: A microelectromechanical switch includes a substrate, an insulator layer disposed outwardly from the substrate, and an electrode disposed outwardly from the insulator layer. The switch also includes a dielectric layer disposed outwardly from the insulator layer and the electrode, the dielectric layer having a dielectric constant of greater than or equal to twenty. The switch also includes a membrane layer disposed outwardly from the dielectric layer, the membrane layer overlying a support layer, the support layer operable to space the membrane layer outwardly from the dielectric layer.

Abstract: The present invention provides a method and product-by-method of integrating a bias resistor in circuit with a bottom electrode of a micro-electromechanical switch on a silicon substrate. The resistor and bottom electrode are formed simultaneously by first sequentially depositing a layer of a resistor material (320), a hard mask material (330) and a metal material (340) on a silicon substrate forming a stack. The bottom electrode and resistor lengths are subsequently patterned and etched (350) followed by a second etching (360) process to remove the hard mask and metal materials from the defined resistor length. Finally, in a preferred embodiment, the bottom electrode and resistor structure is encapsulated with a layer of dielectric which is patterned and etched (370) to correspond to the defined bottom electrode and resistor.

Abstract: A rugged polysilicon electrode for a capacitor has high surface area enhancement with a thin layer by high nucleation density plus gas phase doping which also enhances grain shape and oxygen-free dielectric formation.

Abstract: The present invention includes an integrated circuit switch including a membrane supported over a first conductor on a substrate, a conductive region on the membrane and connecting to the first conductor on the substrate, a pulldown electrode on the substrate and under the membrane and a pillar to support the membrane after the pulldown threshold has been reached. A voltage greater than a pulldown threshold is applied between the membrane and the pulldown electrode will pull the membrane down to make a capacitive coupling to the first conductor. The addition of the pillars increases the upward restoring force when the activation voltage is removed.

Abstract: A microelectromechanical switch includes a substrate, an insulator layer disposed outwardly from the substrate, and an electrode disposed outwardly from the insulator layer. The switch also includes a dielectric layer disposed outwardly from the insulator layer and the electrode, the dielectric layer having a dielectric constant of greater than or equal to twenty. The switch also includes a membrane layer disposed outwardly from the dielectric layer, the membrane layer overlying a support layer, the support layer operable to space the membrane layer outwardly from the dielectric layer.

Abstract: A method for forming a dynamic random access memory with increased capacitance includes preparing (36) ultra-fine particles in a microemulsion. The particles are deposited (38) on the lower electrode layer of the memory cell. A micro-villus pattern is then formed (40) on the lower electrode layer, using the particles as a mask. A layer of HSG polysilicon may then be deposited (42) on the micro-villus pattern. A dielectric and upper electrode are then formed (44) overlying the lower electrode to form a storage capacitor for the dynamic random access memory.

Abstract: A microelectromechanical switch includes a substrate, an insulator layer disposed outwardly from the substrate, and an electrode disposed outwardly from the insulator layer. The switch also includes a dielectric layer disposed outwardly from the insulator layer and the electrode, the dielectric layer having a dielectric constant of greater than or equal to twenty. The switch also includes a membrane layer disposed outwardly from the dielectric layer, the membrane layer overlying a support layer, the support layer operable to space the membrane layer outwardly from the dielectric layer.

Abstract: The present invention provides a method and product-by-method of integrating a bias resistor in circuit with a bottom electrode of a micro-electromechanical switch on a silicon substrate. The resistor and bottom electrode are formed simultaneously by first sequentially depositing a layer of a resistor material (320), a hard mask material (330) and a metal material (340) on a silicon substrate forming a stack. The bottom electrode and resistor lengths are subsequently patterned and etched (350) followed by a second etching (360) process to remove the hard mask and metal materials from the defined resistor length. Finally, in a preferred embodiment, the bottom electrode and resistor structure is encapsulated with a layer of dielectric which is patterned and etched (370) to correspond to the defined bottom electrode and resistor.

Abstract: A post-in-crown capacitor is disclosed. The post-in-crown capacitor (60) includes a crown (44) coupled to a conductive via (20). A post (48) is disposed within the crown (44) and a capacitor insulation layer (50) is formed outwardly from the crown (44) and the post (48). A capacitor plate layer (52) is then formed outwardly from the capacitor insulation layer (50).

Abstract: The present invention includes an integrated circuit switch including a membrane supported over a first conductor on a substrate, a conductive region on the membrane and connecting to the first conductor on the substrate, a pulldown electrode on the substrate and under the membrane and a pillar to support the membrane after the pulldown threshold has been reached. A voltage greater than a pulldown threshold is applied between the membrane and the pulldown electrode will pull the membrane down to make a capacitive coupling to the first conductor. The addition of the pillars increases the upward restoring force when the activation voltage is removed.

Abstract: A post-in-crown capacitor is disclosed. The post-in-crown capacitor (60) includes a crown (44) coupled to a conductive via (20). A post (48) is disposed within the crown (44) and a capacitor insulation layer (50) is formed outwardly from the crown (44) and the post (48). A capacitor plate layer (52) is then formed outwardly from the capacitor insulation layer (50).

Abstract: A Micro Electro-Mechanical System (MEMS) switch (100) having a bottom electrode (116) formed over a substrate (112) and a thin protective cap layer (130) disposed over the bottom electrode (116). A dielectric material (118) is disposed over the protective cap layer (130) and a pull-down electrode (122) is formed over the spacer (120) and the dielectric material (118). The protective cap layer (130) prevents the oxidation of the bottom electrode (116). The thin protective cap layer (130) comprises a metal having an associated oxide with a high dielectric constant. A portion (132) of the thin protective cap layer (130) may oxidize during the formation of the dielectric material (118), increasing the capacitance of the dielectric stack (128).

Abstract: A microelectromechanical switch includes a substrate, an insulator layer disposed outwardly from the substrate, and an electrode disposed outwardly from the insulator layer. The switch also includes a dielectric layer disposed outwardly from the insulator layer and the electrode, the dielectric layer having a dielectric constant of greater than or equal to twenty. The switch also includes a membrane layer disposed outwardly from the dielectric layer, the membrane layer overlying a support layer, the support layer operable to space the membrane layer outwardly from the dielectric layer.

Abstract: A rugged polysilicon electrode for a capacitor has high surface area enhancement with a thin layer by high nucleation density plus gas phase doping which also enhances grain shape and oxygen-free dielectric formation.

Abstract: A planarized capacitor array (182) and method of forming the same for high density applications. A storage node contact (116) is formed through an interlevel dielectric (110) on a semiconductor body (102). Then, an oxide layer (170) having a first thickness is deposited over the interlevel dielectric (110) and the storage node contact (116). A nitride layer (172) having a second thickness is deposited over the oxide layer (170) to protect the oxide layer (170) during later processing. The nitride layer (172) and oxide layer (170) are then patterned and etched to form a storage plate cavity (180). The capacitor array (182) is then formed in the storage plate cavity (180). The capacitor array (182) has a height approximately equal to the sum of said first and second thicknesses, so that the surface of the top node of the capacitor array (182) is co-planar with the upper surface of the surrounding oxide/nitride stack (170/172).