Abstract: An apparatus having a circuit. The circuit may be configured to (i) calculate a plurality of complexity values while compressing a current picture in a video signal. Each complexity value generally characterizes how a corresponding one of a plurality of blocks in the current picture was compressed. The circuit may also be configured to (ii) adjust the complexity values below a first threshold to a default value and (iii) generate a region of interest by grouping the blocks having non-default values of the complexity values above a second threshold.

Abstract: An apparatus comprising a decision circuit, a detector circuit and a processing circuit. The decision circuit may be configured to generate a confirmation signal in response to a first lock signal and a second lock signal. The detector circuit may be configured to generate the first lock signal in response to a filtered version of an input signal being above a threshold. The processing circuit may be configured to generate the second lock signal in response to a power signal received from the detector circuit. The processing circuit generates the second lock signal by analyzing the rising edge of a frequency power envelope of the power signal.

Abstract: An apparatus having a plurality of processors is disclosed. The processors may be configured to (i) gather a plurality of statistics by encoding a current picture in a video signal, (ii) calculate a plurality of complexity values in response to both the statistics and a plurality of coefficients and (iii) partition a next picture in the video signal into a plurality of slices in response to the complexity values such that each of the slices has a similar coding complexity. The statistics generally characterize how the current picture was encoded. The coefficients may correspond to a plurality of coding modes.

Abstract: An apparatus comprising a decision circuit, a detector circuit and a processing circuit. The decision circuit may be configured to generate a confirmation signal in response to a first lock signal and a second lock signal. The detector circuit may be configured to generate the first lock signal in response to a filtered version of an input signal being above a threshold. The processing circuit may be configured to generate the second lock signal in response to a power signal received from the detector circuit. The processing circuit generates the second lock signal by analyzing the rising edge of a frequency power envelope of the power signal.

Abstract: An apparatus comprising a decision circuit, a detector circuit and a processing circuit. The decision circuit may be configured to generate a confirmation signal in response to a first lock signal and a second lock signal. The detector circuit may be configured to generate the first lock signal in response to a filtered version of an input signal being above a threshold. The processing circuit may be configured to generate the second lock signal in response to a power signal received from the detector circuit. The processing circuit generates the second lock signal by analyzing the rising edge of a frequency power envelope of the power signal.

Abstract: An apparatus having a circuit is disclosed. The circuit may be configured to (i) generate a complexity value by encoding a current picture in a video signal, where the current picture is encoded using a current one of a plurality of configurations, (ii) calculate an estimate in response to the complexity value and (iii) reconfigure the encoding into a new one of the configurations in response to the estimate relative to one or more thresholds. The configurations may include a normal configuration and one or more simplified configurations. The estimate generally describes a computational stress that the encoding of the current picture placed on the circuit. The new configuration may be different from the current configuration.

Abstract: An apparatus comprising a decision circuit, a detector circuit and a processing circuit. The decision circuit may be configured to generate a confirmation signal in response to a first lock signal and a second lock signal. The detector circuit may be configured to generate the first lock signal in response to a filtered version of an input signal being above a threshold. The processing circuit may be configured to generate the second lock signal in response to a power signal received from the detector circuit. The processing circuit generates the second lock signal by analyzing the rising edge of a frequency power envelope of the power signal.

Abstract: An apparatus having a circuit is disclosed. The circuit may be configured to (i) calculate a plurality of complexity values while compressing a current picture in a video signal. Each complexity value generally characterizes how a corresponding one of a plurality of blocks in the current picture was compressed. The circuit may also be configured to (ii) adjust the complexity values below a first threshold to a default value and (iii) generate a region of interest by grouping the blocks having non-default values of the complexity values above a second threshold.

Abstract: An apparatus having a circuit is disclosed. The circuit may be configured to (i) generate a complexity value by encoding a current picture in a video signal, where the current picture is encoded using a current one of a plurality of configurations, (ii) calculate an estimate in response to the complexity value and (iii) reconfigure the encoding into a new one of the configurations in response to the estimate relative to one or more thresholds. The configurations may include a normal configuration and one or more simplified configurations. The estimate generally describes a computational stress that the encoding of the current picture placed on the circuit. The new configuration may be different from the current configuration.

Abstract: An apparatus having a memory and a circuit is disclosed. The memory may be configured to store multiple reference pictures. The circuit may be configured to (i) generate multiple compressed pictures by compressing each uncompressed picture using the reference pictures and a constant-bit budget and (ii) generate multiple new reference pictures in the memory by decompressing the compressed pictures. A subset of the compressed pictures may each be divided into a first area, a second area and a third area. The first areas are generally intra-encoded. Each motion vector of the second areas in the compressed pictures may point outside the third areas of the reference pictures. The first areas in the reference pictures that were decompressed from the subset of the compressed pictures may incorporate content from the third areas.

Abstract: An apparatus having a plurality of processors is disclosed. The processors may be configured to (i) gather a plurality of statistics by encoding a current picture in a video signal, (ii) calculate a plurality of complexity values in response to both the statistics and a plurality of coefficients and (iii) partition a next picture in the video signal into a plurality of slices in response to the complexity values such that each of the slices has a similar coding complexity. The statistics generally characterize how the current picture was encoded. The coefficients may correspond to a plurality of coding modes.