Abstract: A method and apparatus for conversion of a time interval to a digital word, the time interval being mapped to a difference of a length of a reference time and a length of a signal time. Reference time is generated from an instant when the beginning of the time interval is detected, and the signal time is generated from an instant when the end of the time interval is detected by the use the control module. The generation of the reference time and the signal time is terminated at the same instant. In the apparatus, bottom plates of capacitors of the set of capacitors are connected to a ground of the circuit, and top plates of these capacitors are connected, respectively, to moving contacts of change-over switches. First, second, and third stationary contacts are connected to the signal rail, the ground of the circuit, and to the reference rail.

Abstract: A method for indirect conversion of a voltage value to a digital word consisting in sampling an input voltage through a parallel connection of a sampling capacitor to a source of the input voltage, and next in mapping a sample value of the input voltage to a time interval, and in assignment of a corresponding value of n-bit output digital word by the use a control module characterized in that the time interval is mapped to a difference of a length of a reference time and a length of a signal time, while the reference time is generated from an instant when the beginning of the time interval is detected by the use the control module, and the signal time is generated from an instant when the end of the time interval is detected by the use the control module, whereas generation of the reference time and the signal time is terminated at the same instant.

Abstract: Method for encoding analog signal into time intervals wherein a generation of time intervals using a time encoding machine. A signal of a constant value is held during a generated time interval on a time encoding machine input by the use of a sample-and-hold circuit, while the constant value of the signal held during the generated time interval represents an instantaneous value of the analog signal at the end of a generation of a previous time interval. Apparatus for encoding analog signal into time intervals comprising a time encoding machine, and a sample-and-hold circuit. The signal is provided to an input of the sample-and-hold circuit, whose output is connected to an output of the time encoding machine. The output of the time encoding machine is connected to an output of the apparatus, and to a control input of the sample-and-hold circuit.

Abstract: A method and apparatus for conversion of a time interval to a digital word, the time interval being mapped to a difference of a length of a reference time and a length of a signal time. Reference time is generated from an instant when the beginning of the time interval is detected, and the signal time is generated from an instant when the end of the time interval is detected by the use the control module. The generation of the reference time and the signal time is terminated at the same instant. In the apparatus, bottom plates of capacitors of the set of capacitors are connected to a ground of the circuit, and top plates of these capacitors are connected, respectively, to moving contacts of change-over switches First, second, and third stationary contacts are connected to the signal rail, the ground of the circuit, and to the reference rail.

Abstract: A method and apparatus for conversion of a time interval to a digital word, the time interval being mapped to a difference of a length of a reference time and a length of a signal time. Reference time is generated from an instant when the beginning of the time interval is detected, and the signal time is generated from an instant when the end of the time interval is detected by the use the control module. The generation of the reference time and the signal time is terminated at the same instant. In the apparatus, bottom plates of capacitors of the set of capacitors are connected to a ground of the circuit, and top plates of these capacitors are connected, respectively, to moving contacts of change-over switches. First, second, and third stationary contacts are connected to the signal rail, the ground of the circuit, and to the reference rail (R).

Abstract: Method for conversion of a value of an analog signal to a compressed digital word uses conversion of the analog signal to a linear digital word according to a successive approximation scheme. The process of conversion of the analog signal to the linear digital word is terminated by the compression module when all bits of the compression word have been already evaluated. Apparatus for conversion of a value of an analog signal to a compressed digital word a linear successive approximation analog-to-digital converter. The output of the linear digital word of this converter is connected to the input of the linear digital word of the compression module comprising a section number register, while complete conversion signal output of the compression module is connected to a complete conversion signal input of the linear analog-to-digital converter, and a bit ready signal output of the linear analog-to-digital converter is connected to a bit ready signal input of the compression module.

Abstract: A method for indirect conversion of a voltage value to a digital word consisting in sampling an input voltage through a parallel connection of a sampling capacitor to a source of the input voltage, and next in mapping a sample value of the input voltage to a time interval, and in assignment of a corresponding value of n-bit output digital word by the use a control module characterized in that the time interval is mapped to a difference of a length of a reference time and a length of a signal time, while the reference time is generated from an instant when the beginning of the time interval is detected by the use the control module, and the signal time is generated from an instant when the end of the time interval is detected by the use the control module, whereas generation of the reference time and the signal time is terminated at the same instant.

Abstract: Method for encoding analog signal into time intervals wherein a generation of time intervals using a time encoding machine. A signal of a constant value is held during a generated time interval on a time encoding machine input by the use of a sample-and-hold circuit, while the constant value of the signal held during the generated time interval represents an instantaneous value of the analog signal at the end of a generation of a previous time interval. Apparatus for encoding analog signal into time intervals comprising a time encoding machine, and a sample-and-hold circuit. The signal is provided to an input of the sample-and-hold circuit, whose output is connected to an output of the time encoding machine. The output of the time encoding machine is connected to an output of the apparatus, and to a control input of the sample-and-hold circuit.

Abstract: The solution according to the invention consisting in conversion of a time interval to a digital word of a number of bits equal to n by the use of the array (A) of binary-scaled capacitors (Cn-1, . . . , C0) is characterized in that the time interval whose both start and end are detected by the control module (CM) is first mapped to a portion of electric charge delivered by the current source (I) and successively accumulated in the capacitors ((Cn-1, . . . , C0)) in the order of decreasing capacitances starting from the capacitor (Cn-1) having the highest capacitance value in the array, and when the control module (CM) detects the end of the time interval, the charge accumulated in the capacitor (Cx) charged recently is successively transferred by the use of the current source (I) to the capacitors of lower capacitance values.

Abstract: The method includes the accumulation of electric charge in the sampling capacitor (Cn) by parallel connection of the sampling capacitor (Cn) to the source of converted voltage (UIN) and in realization of the process of charge redistribution in the array of redistribution (A) by changing states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module (CM). After detection of the beginning of the next trigger signal (Px+1), the charge is accumulated in the additional sampling capacitor (CnA), and then the process of charge redistribution is realized and relevant values are assigned to bits of the digital word. The apparatus includes an array of redistribution (A), the section of the sampling capacitor (An), the control module (CM), two comparators (K1 and K2) and the current source (J) connected in a known way.

Abstract: The solution according to the invention consisting in conversion of a voltage value to a digital word of a number of bits equal to n is characterized in that the converted voltage value is first mapped to a portion of electric charge accumulated in the sampling capacitor (C-n) during the active state of the signal on the trigger input (InS) and the accumulated charge portion is next successively redistributed by the use of the current source (I) in the array (A) of binary-scaled capacitors (Cn-1, . . . , C0) in the order of decreasing capacitances starting from the capacitor (Cn-1) having the highest capacitance value in the array (A). The process of charge redistribution is controlled by the control module (CM) on the basis of the output signals of the comparators (K1) and (K2) without the use of a clock while the value one is assigned to these bits (bn-1, . . . , b0) in the digital output word that correspond to the capacitors (Cn-1, . . .

Abstract: The solution according to the invention consisting in conversion of a portion of electric charge to a digital word of a number of bits equal to n by the use of successive redistribution of charge in the array (A) of binary-scaled capacitors (Cn-1, . . . , Co) is characterized in that charge is first accumulated during the active state of the external gate signal on the gate signal input (InG) in the capacitors (Cn-1, . . . , Co) in the order of decreasing capacitances starting from the capacitor (Cn-1) having the highest capacitance value in the array, and when the active state of the gate signal is terminated, the charge accumulated in the capacitor (Cx) charged recently is successively transferred by the use of the current source (I) to the capacitors of lower capacitance values. The process of charge transfer is controlled by the control module (CM) on the basis of the output signals of the comparators (K1) and (K2) without the use of a clock while the value one is assigned to these bits (bn-1, . . .

Abstract: Method and apparatus for mapping the converted voltage value by electric charge value proportional to the converted voltage value and in accumulation of charge in the sampling capacitor until the voltage on this capacitor is equal to the converted voltage. Furthermore, realization of the process of that electric charge redistribution in the array of redistribution by changes of states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module. As soon as accumulation of electric charge in the sampling capacitor is terminated, electric charge is accumulated in the additional sampling capacitor then the process of that electric charge redistribution is realized and relevant values are assigned to bits of the digital word. When a trigger signal is detected, next cycle begins and electric charge is accumulated in the sampling capacitor.

Abstract: A conversion module contains an asynchronous analog-to-digital converter (AADC) with the output signal generated at irregular time intervals, whose output is connected to the input of the buffer memory module (BUF), and the output of the buffer memory module (BUF) is connected through the internal bus (BUS) simultaneously to the source address module (SADR), to the configuration registers module (REG), to the control module of the interface (CM), which the reference generator (RG) is connected to, and to the destination address module (DADR), to the selection register module (SELREG), to the transmitter/receiver module (SDM), and moreover the control inputs/outputs (1, 2, . . .

Abstract: Method and apparatus for accumulation of electric charge delivered to the charge input (InQ) in the sampling capacitor (Cn) and in realization of the process of charge redistribution in the array of redistribution (A) by changing states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module (CM). Method is characterized in that after detection of the beginning of the next gate signal (Gx+1), the charge is accumulated in the additional sampling capacitor (CnA), and then the process of charge redistribution is realized and relevant values are assigned to bits of the digital word. When the beginning of the subsequent gate signal (Gx+2) is detected, the next cycle begins and electric charge is accumulated in the sampling capacitor (Cn) again.

Abstract: Method and apparatus for detecting the beginning and end of a time interval using the control module and in mapping this time interval to a portion of electric charge proportional to this time interval and accumulated in the sampling capacitor and then realizing the process of charge redistribution in the array of redistribution by changing states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module. After detection of the beginning of the next time interval, the charge is accumulated in the additional sampling capacitor and then the process of charge redistribution is realized and relevant values are assigned to bits of the digital word. When the beginning of the subsequent time interval is detected, the next cycle begins and electric charge is accumulated in the sampling capacitor again.

Abstract: The solution according to the invention consisting in conversion of a time interval to a digital word of a number of bits equal to n by the use of the array (A) of binary-scaled capacitors (C.n-1, . . . , C0) is characterized in that the time interval whose both start and end are detected by the control module (CM) is first mapped to a portion of electric charge delivered by the current source (I) and successively accumulated in the capacitors ((Cn-1, . . . , C0)) in the order of decreasing capacitances starting from the capacitor (Cn-1) having the highest capacitance value in the array, and when the control module (CM) detects the end of the time interval, the charge accumulated in the capacitor (Cx) charged recently is successively transferred by the use of the current source (I) to the capacitors of lower capacitance values.

Abstract: Method and apparatus for accumulation of electric charge delivered to the charge input (InQ) in the sampling capacitor (Cn) and in realization of the process of charge redistribution in the array of redistribution (A) by changing states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module (CM). Method is characterized in that after detection of the beginning of the next gate signal (Gx+1), the charge is accumulated in the additional sampling capacitor (CnA), and then the process of charge redistribution is realized and relevant values are assigned to bits of the digital word. When the beginning of the subsequent gate signal (Gx+2) is detected, the next cycle begins and electric charge is accumulated in the sampling capacitor (Cn) again.

Abstract: Method and apparatus for detecting the beginning and end of a time interval using the control module and in mapping this time interval to a portion of electric charge proportional to this time interval and accumulated in the sampling capacitor and then realizing the process of charge redistribution in the array of redistribution by changing states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module. After detection of the beginning of the next time interval, the charge is aaccumulated in the additional sampling capacitor and then the process of charge redistribution is realized and relevant values are assigned to bits of the digital word. When the beginning of the subsequent time interval is detected, the next cycle begins and electric charge is accumulated in the sampling capacitor again.

Abstract: Method consists in accumulation of electric charge in the sampling capacitor (Cn) by parallel connection of the sampling capacitor (Cn) to the source of converted voltage (UIN) and in realization of the process of charge redistribution in the array of redistribution (A) by changing states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module (CM). Method is characterized in that after detection of the beginning of the next trigger signal (Px+1), the charge is accumulated in the additional sampling capacitor (CnA), and then the process of charge redistribution is realized and relevant values are assigned to bits of the digital word. When the beginning of the subsequent trigger signal (Px+2) is detected, the next cycle begins and electric charge is accumulated in the sampling capacitor (Cn) again.