Patents by Inventor Dariusz Kowalczyk
Dariusz Kowalczyk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9183921Abstract: A method includes coupling, by using a switching circuit, a first node to a bulk node of an input/output (IO) circuit of a memory circuit when the IO circuit operates in an active mode. The first node is configured to carry a first voltage level sufficient to cause a set of transistors of the IO circuit to have a first threshold voltage. A second node is coupled to the bulk node by using the switching circuit when the IO circuit operates in an inactive mode. The second node is configured to carry a second voltage level sufficient to cause the set of transistors of the IO circuit to have a second threshold voltage, and an absolute value of the second threshold voltage is greater than an absolute value of the first threshold voltage.Type: GrantFiled: November 13, 2014Date of Patent: November 10, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Dariusz Kowalczyk
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Publication number: 20150071015Abstract: A method includes coupling, by using a switching circuit, a first node to a bulk node of an input/output (IO) circuit of a memory circuit when the IO circuit operates in an active mode. The first node is configured to carry a first voltage level sufficient to cause a set of transistors of the IO circuit to have a first threshold voltage. A second node is coupled to the bulk node by using the switching circuit when the IO circuit operates in an inactive mode. The second node is configured to carry a second voltage level sufficient to cause the set of transistors of the IO circuit to have a second threshold voltage, and an absolute value of the second threshold voltage is greater than an absolute value of the first threshold voltage.Type: ApplicationFiled: November 13, 2014Publication date: March 12, 2015Inventor: Dariusz KOWALCZYK
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Patent number: 8908459Abstract: A circuit includes an input/output (IO) circuit, a first node configured to have a first voltage level, a second node configured to have a second voltage level, a third node, and a switching circuit. The IO circuit has a set of transistors, and the third node is coupled to bulks of the set of transistors. The switching circuit is configured to couple the first node to the third node when the IO circuit is operated in an active mode; and couple the second node to the third node when the IO circuit is operated in an inactive mode. The first voltage level causes the set of transistors to have a first threshold voltage, the second voltage level causes the set of transistors to have a second threshold voltage, and an absolute value of the second threshold voltage is greater than that of the first threshold voltage.Type: GrantFiled: August 28, 2013Date of Patent: December 9, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Dariusz Kowalczyk
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Publication number: 20130343138Abstract: A circuit includes an input/output (IO) circuit, a first node configured to have a first voltage level, a second node configured to have a second voltage level, a third node, and a switching circuit. The IO circuit has a set of transistors, and the third node is coupled to bulks of the set of transistors. The switching circuit is configured to couple the first node to the third node when the IO circuit is operated in an active mode; and couple the second node to the third node when the IO circuit is operated in an inactive mode. The first voltage level causes the set of transistors to have a first threshold voltage, the second voltage level causes the set of transistors to have a second threshold voltage, and an absolute value of the second threshold voltage is greater than that of the first threshold voltage.Type: ApplicationFiled: August 28, 2013Publication date: December 26, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Dariusz KOWALCZYK
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Patent number: 8542551Abstract: A circuit comprises a first voltage source, a second voltage source, a first switch, firsts transistors, and a control circuitry. The first switch is configured to selectively couple the first voltage source or the second voltage source to a first signal line. The first transistors are in an IO circuitry and have first bulks configured to receive the first signal line. The control circuitry is configured to receive a clock and a command signal on a command signal line, and generate a first control signal on a first control signal line to control the first switch based on the clock and the command signal.Type: GrantFiled: July 29, 2011Date of Patent: September 24, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Dariusz Kowalczyk
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Publication number: 20130028031Abstract: A circuit comprises a first voltage source, a second voltage source, a first switch, firsts transistors, and a control circuitry. The first switch is configured to selectively couple the first voltage source or the second voltage source to a first signal line. The first transistors are in an IO circuitry and have first bulks configured to receive the first signal line. The control circuitry is configured to receive a clock and a command signal on a command signal line, and generate a first control signal on a first control signal line to control the first switch based on the clock and the command signal.Type: ApplicationFiled: July 29, 2011Publication date: January 31, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Dariusz KOWALCZYK
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Patent number: 6894941Abstract: A row addressing circuit for DRAM memory is disclosed. Additional address or mode bits are used to dynamically select between long page and short page access modes, and to dynamically select between single cell per bit and dual, or two cell per bit modes in each memory bank within a memory block. In the short page access mode, only one wordline in a memory block is activated. In the long page access mode, two wordlines in the memory block are activated for accessing twice the number of bits as in short page access mode. In the single cell per bit mode, one bit of data is stored in one DRAM cell. In the two cell per bit mode, the row addressing circuit simultaneously activates two wordlines in a bank of the memory block to access one DRAM cell connected to each bitline of a pair of complementary bitlines for writing and reading complementary data. The row addressing circuit can combine the different access modes for system design flexibility.Type: GrantFiled: December 3, 2002Date of Patent: May 17, 2005Assignee: Atmos CorporationInventors: Wlodek Kurjanowicz, Jacek Wiatrowski, Dariusz Kowalczyk, Greg Popoff
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Publication number: 20030086316Abstract: A row addressing circuit for DRAM memory is disclosed. Additional address or mode bits are used to dynamically select between long page and short page access modes, and to dynamically select between single cell per bit and dual, or two cell per bit modes in each memory bank within a memory block. In the short page access mode, only one wordline in a memory block is activated. In the long page access mode, two wordlines in the memory block are activated for accessing twice the number of bits as in short page access mode. In the single cell per bit mode, one bit of data is stored in one DRAM cell. In the two cell per bit mode, the row addressing circuit simultaneously activates two wordlines in a bank of the memory block to access one DRAM cell connected to each bitline of a pair of complementary bitlines for writing and reading complementary data. The row addressing circuit can combine the different access modes for system design flexibility.Type: ApplicationFiled: December 3, 2002Publication date: May 8, 2003Inventors: Wlodek Kurjanowicz, Jacek Wiatrowski, Dariusz Kowalczyk, Greg Popoff
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Patent number: 6549483Abstract: A row addressing circuit for DRAM memory is disclosed. Additional address or mode bits are used to dynamically select between long page and short page access modes, and to dynamically select between single cell per bit and dual, or two cell per bit modes in each memory bank within a memory block. In the short page access mode, only one wordline in a memory block is activated. In the long page access mode, two wordlines in the memory block are activated for accessing twice the number of bits as in short page access mode. In the single cell per bit mode, one bit of data is stored in one DRAM cell. In the two cell per bit mode, the row addressing circuit simultaneously activates two wordlines in a bank of the memory block to access one DRAM cell connected to each bitline of a pair of complementary bitlines for writing and reading complementary data. The row addressing circuit can combine the different access modes for system design flexibility.Type: GrantFiled: April 1, 2002Date of Patent: April 15, 2003Assignee: ATMOS CorporationInventors: Wlodek Kurjanowicz, Jacek Wiatrowski, Dariusz Kowalczyk, Greg Popoff
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Publication number: 20020176311Abstract: A row addressing circuit for DRAM memory is disclosed. Additional address or mode bits are used to dynamically select between long page and short page access modes, and to dynamically select between single cell per bit and dual, or two cell per bit modes in each memory bank within a memory block. In the short page access mode, only one wordline in a memory block is activated. In the long page access mode, two wordlines in the memory block are activated for accessing twice the number of bits as in short page access mode. In the single cell per bit mode, one bit of data is stored in one DRAM cell. In the two cell per bit mode, the row addressing circuit simultaneously activates two wordlines in a bank of the memory block to access one DRAM cell connected to each bitline of a pair of complementary bitlines for writing and reading complementary data. The row addressing circuit can combine the different access modes for system design flexibility.Type: ApplicationFiled: April 1, 2002Publication date: November 28, 2002Inventors: Wlodek Kurjanowicz, Jacek Wiatrowski, Dariusz Kowalczyk, Greg Popoff