Abstract: Substrate assemblies having adhesion promotor layers and related methods are disclosed. An example package assembly includes a substrate, a dielectric layer and a conductive layer between the substrate and the dielectric layer. The conductive layer has a surface roughness of less than 1 micrometer (?m). A film is provided between the dielectric layer and the conductive layer, and between exposed surfaces of the substrate adjacent the conductive layer and the dielectric layer. The film including silicon and nitrogen and being substantially free of hydrogen.

Abstract: Embodiments herein relate to systems, apparatuses, or processes for forming a silicide and a silicon nitrate layer between a copper feature and dielectric to reduce delamination of the dielectric. Embodiments allow an unroughened surface for the copper feature to reduce the insertion loss for transmission lines that go through the unroughened surface of the copper. Embodiments may include sequential interlayers between a dielectric and copper. Other embodiments may be described and/or claimed.

Abstract: Embodiments disclosed herein include package substrates and methods of forming such substrates. In an embodiment, a package substrate comprises a core, a first layer over the core, where the first layer comprises a metal, and a second layer over the first layer, where the second layer comprises an electrical insulator. In an embodiment, the package substrate further comprises a third layer over the second layer, where the third layer comprises a dielectric material, and where an edge of the core extends past edges of the first layer, the second layer, and the third layer.

Abstract: High-density IC die package routing structures with one or more nitrided surfaces. Metallization features may be formed, for example with a plating process. Following the plating process, a surface of the metallization features may be exposed to a surface treatment that incorporates nitrogen onto a surface of the metallization. The presence of nitrogen may chemically improve adhesion between finely patterned metallization features and package dielectric material. Accordingly, surface roughness of metallization features may be reduced without suffering delamination. With lower surface roughness, metallization features may transmit higher frequency data signals with lower insertion loss.

Abstract: Substrates with nitrided glass cores, and methods of forming the same, are described herein. In one example, a substrate includes one or more glass layers and a plurality of dielectric layers. At least one of the glass layers includes nitrogen. Further, at least one of the dielectric layers is above the one or more glass layers and at least one of the dielectric layers is below the one or more glass layers.

Abstract: IC die package routing structures including a bulk layer of a first metal composition on an underlying layer of a second metal composition. The lower layer may be sputter deposited to a thickness sufficient to support plating of the bulk layer upon a first portion of the lower layer. Following the plating process, a second portion of the lower layer may be removed selectively to the bulk layer. Multiple IC die may be attached to the package with the package routing structures responsible for the transmission of high-speed data signals between the multiple IC die. The package may be further assembled to a host component that conveys power to the IC die package.

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to an organic adhesion promoter layer on the surface of a copper trace to reduce delamination between a dielectric material and the surface of the copper trace, and to facilitate a smooth surface interface between the surface of the copper trace and of a copper feature, such as a copper-filled via, placed on the surface of the copper trace. The smooth surface interface reduces insertion loss and enables routing of higher frequency signals on a package, and does not require roughing of the copper trace in order to adhere to the dielectric material. Other embodiments may be described and/or claimed.

Abstract: Techniques for thin-film resistors in vias are disclosed. In the illustrative embodiment, thin-film resistors are formed in through-glass vias of a glass substrate of an interposer. The thin-film resistors do not take up a significant amount of area on a layer of the interposer, as the thin-film resistor extends vertically through a via rather than horizontally on a layer of the interposer. The thin-film resistors may be used for any suitable purpose, such as power dissipation or voltage control, current control, as a pull-up or pull-down resistor, etc.

Abstract: Embodiments disclosed herein include electronic packages with a ground plate embedded in the solder resist that extends over signal traces. In an embodiment, the electronic package comprises a substrate layer, a trace over the substrate layer, and a first pad over the substrate layer. In an embodiment, a solder resist is disposed over the trace and the first pad. In an embodiment a trench is formed into the solder resist, and the trench extends over the trace. In an embodiment, a conductive plate is disposed in the trench, and is electrically coupled to the first pad by a via that extends from a bottom surface of the trench through the solder resist.

Abstract: The present disclosure is directed to a monitoring system for a plating process using a monitoring device including a metrology component for collecting agitation intensity data on at least one agitation component within a plating equipment and transferring the collected agitation intensity data to a process control station.

Abstract: A microelectronic structure and a method of forming same. The microelectronic structure includes: a core substrate including one of a glass material or an organic material, and defining a plurality of trenches therein; electrically conductive vias extending within the trenches, the vias to provide electrical coupling through the core substrate to semiconductor packages to be attached to the core substrate, individual ones of the vias including: a trench liner adjacent walls of a corresponding one of the plurality of trenches, the trench liner including an electrically conductive polymer material having double carbon bonds; and a metal structure on the trench liner.

Abstract: Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a dielectric having a cavity that has a footprint, a resistor embedded in the cavity of the dielectric, and a plurality of traces on the resistor, where a plurality of surfaces of the resistor are activated surfaces. The resistor may also have a plurality of sidewalls which may be activated sidewalls and tapered. The dielectric may include metallization particles/ions. The resistor may include resistive materials, such as nickel-phosphorus (NiP), aluminum-nitride (AlN), and/or titanium-nitride (TiN). The package substrate may further include a first resistor embedded adjacently to the resistor. The first resistor may have a first footprint of a first cavity that is different than the footprint of the cavity of the resistor. The resistor may have a resistance value that is thus different than a first resistance value of the first resistor.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to glass layers within a package that include one or more high aspect ratio TGV that are filled with conductive material. The TGV extends from a first side of the glass layer to a second side of the glass layer opposite the first side and are filled with conductive material to provide a high-quality electrical connection between the first side of the glass layer and the second side of the glass layer, where a portion of the wall of the TGV includes titanium. Other embodiments may be described and/or claimed.

Abstract: Glass substrates having transverse capacitors for use with semiconductor packages and related methods are disclosed. An example semiconductor package includes a glass substrate having a through glass via between a first surface and a second surface opposite the first surface. A transverse capacitor is located in the through glass via. The transverse capacitor includes a dielectric material positioned in a first portion of the through glass via, a first barrier/seed layer positioned in a second portion of the through glass via, and a first conductive material positioned in a third portion of the through glass via.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to embedding capacitors in through glass vias within a glass core of a substrate. In embodiments, the through glass vias may extend entirely from a first side of the glass core to a second side of the glass core opposite the first side. Layers of electrically conductive material and dielectric material may then be deposited within the through glass via to form a capacitor. the capacitor may then be electrically coupled with electrical routings on buildup layers on either side of the glass core. Other embodiments may be described and/or claimed.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a first layer, where the first layer comprises glass. In an embodiment, a second layer is over the first layer, where the second layer comprises a mold material. In an embodiment, a first photonics integrated circuit (PIC) is within the second layer. In an embodiment, a second PIC is within the second layer, and a waveguide is in the first layer. In an embodiment, the waveguide optically couples the first PIC to the second PIC.

Abstract: An electronic device comprises an electronic package with a glass core. The glass core includes a first surface and a second surface opposite the first surface, at least one through-glass via (TGV) extending through the glass core from the first surface to the second surface and including an electrically conductive material, and wherein the at least one TGV includes a first portion having a first sidewall and a second portion that includes a second sidewall, wherein the first sidewall includes seed metallization and the second sidewall excludes the seed metallization.

Abstract: An electronic device comprises an electronic package with a glass core. The glass core includes a first surface and a second surface opposite the first surface, at least one through-glass via (TGV) extending through the glass core from the first surface to the second surface, and including an electrically conductive material, and wherein the at least one TGV includes a first portion having a first width and a second portion having a second width different from the first width.

Abstract: Embodiments disclosed herein include electronic packages with embedded magnetic materials and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of dielectric layers. In an embodiment a plurality of passive components is located in a first dielectric layer of the plurality of dielectric layers. In an embodiment, first passive components of the plurality of passive components each comprise a first magnetic material, and second passive components of the plurality of passive components each comprise a second magnetic material. In an embodiment, a composition of the first magnetic material is different than a composition of the second magnetic material.

Abstract: Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a self-assembled monolayer (SAM) layer over a first dielectric, where the SAM layer includes first end groups and second end groups. The second end groups may include a plurality of hydrophobic moieties. The package substrate also includes a conductive pad on the first dielectric, where the conductive pad has a bottom surface, a top surface, and a sidewall, and where the SAM layer surrounds and contacts a surface of the sidewall of the conductive pad. The hydrophobic moieties may include fluorinated moieties. The conductive pad includes a copper material, where the top surface of the conductive pad has a surface roughness that is approximately equal to a surface roughness of the as-plated copper material. The SAM layer may have a thickness that is approximately 0.1 nm to 20 nm.