Patents by Inventor Darlene Hamilton
Darlene Hamilton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8941094Abstract: Methods for adjusting and/or limiting the conductivity range of a nanotube fabric layer are disclosed. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via wet chemistry techniques. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via plasma treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via CVD treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via an inert ion gas implant.Type: GrantFiled: September 2, 2010Date of Patent: January 27, 2015Assignee: Nantero Inc.Inventors: C. Rinn Cleavelin, Thomas Rueckes, H. Montgomery Manning, Darlene Hamilton, Feng Gu
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Patent number: 8619450Abstract: A method of adjusting a resistive change element using a reference is disclosed. The method comprises inspecting a resistive change element to determine a first state; comparing the first state to a reference wherein said reference provides stimulus parameters corresponding to a transition from the first state to a second state; and applying the stimulus parameters to the resistive change element. A resistive change memory cell array is also disclosed.Type: GrantFiled: September 1, 2010Date of Patent: December 31, 2013Assignee: Nantero Inc.Inventor: Darlene Hamilton
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Patent number: 8559255Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.Type: GrantFiled: August 8, 2012Date of Patent: October 15, 2013Assignee: Spansion LLCInventors: Sung-Yong Chung, Zhizheng Liu, Yugi Mizuguchi, Xuguang Alan Wang, Yi He, Ming Kwan, Darlene Hamilton, Sung-Chul Lee, Guowei Wang, Nancy Leong
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Publication number: 20120294103Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.Type: ApplicationFiled: August 8, 2012Publication date: November 22, 2012Applicant: SPANSION LLCInventors: Sung-Yong Chung, Zhizheng Liu, Yugi Mizuguchi, Xuguang Alan Wang, Yi He, Ming Kwan, Darlene Hamilton, Sung-Chul Lee, Guowei Wang, Nancy Leong
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Patent number: 8264898Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.Type: GrantFiled: June 9, 2011Date of Patent: September 11, 2012Assignee: Spansion LLCInventors: Sung-Yong Chung, Zhizheng Liu, Yugi Mizuguchi, Xuguang Alan Wang, Yi He, Ming Kwan, Darlene Hamilton, Sung-Chul Lee, Guowei Wang, Nancy Leong
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Publication number: 20120056149Abstract: Methods for adjusting and/or limiting the conductivity range of a nanotube fabric layer are disclosed. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via wet chemistry techniques. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via plasma treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via CVD treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via an inert ion gas implant.Type: ApplicationFiled: September 2, 2010Publication date: March 8, 2012Applicant: NANTERO, INC.Inventors: C. Rinn CLEAVELIN, Thomas RUECKES, H. Montgomery MANNING, Darlene HAMILTON, Feng GU
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Publication number: 20110235412Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.Type: ApplicationFiled: June 9, 2011Publication date: September 29, 2011Applicant: Spansion LLCInventors: Sung-Yong Chung, Zhizheng Liu, Yugi Mizuguchi, Xuguang Alan Wang, Yi He, Ming Kwan, Darlene Hamilton, Sung-Chul Lee, Guowei Wang, Nancy Leong
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Patent number: 8000127Abstract: A method of resetting a resistive change memory element is disclosed. The method comprises performing a series of programming operations—for example, a programming pulse of a predetermined voltage level and pulse width—on a resistive change memory element in order to incrementally increase the resistance of the memory element above some predefined threshold. Prior to each programming operation, the resistive state of the memory element is measured and used to determine the parameters used in that programming operation. If this measured resistance value is above a first threshold value, the memory element is determined to already be in a reset state and no further programming operation is performed. If this measured resistance value is below a second threshold value, this second threshold value being less than the first threshold value, a first set of programming parameters are used within the programming operation.Type: GrantFiled: November 13, 2009Date of Patent: August 16, 2011Assignee: Nantero, Inc.Inventors: Darlene Hamilton, Rinn Cleavelin
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Patent number: 7986562Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.Type: GrantFiled: December 30, 2009Date of Patent: July 26, 2011Assignee: Spansion LLCInventors: Sung-Yong Chung, Zhizheng Liu, Yugi Mizuguchi, Xuguang Alan Wang, Yi He, Ming Kwan, Darlene Hamilton, Sung-Chul Lee, Guowei Wang, Nancy Leong
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Publication number: 20110051499Abstract: A method of adjusting a resistive change element using a reference is disclosed. The method comprises inspecting a resistive change element to determine a first state; comparing the first state to a reference wherein said reference provides stimulus parameters corresponding to a transition from the first state to a second state; and applying the stimulus parameters to the resistive change element. A resistive change memory cell array is also disclosed.Type: ApplicationFiled: September 1, 2010Publication date: March 3, 2011Inventor: Darlene HAMILTON
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Publication number: 20110038195Abstract: A method of resetting a resistive change memory element is disclosed. The method comprises performing a series of programming operations—for example, a programming pulse of a predetermined voltage level and pulse width—on a resistive change memory element in order to incrementally increase the resistance of the memory element above some predefined threshold. Prior to each programming operation, the resistive state of the memory element is measured and used to determine the parameters used in that programming operation. If this measured resistance value is above a first threshold value, the memory element is determined to already be in a reset state and no further programming operation is performed. If this measured resistance value is below a second threshold value, this second threshold value being less than the first threshold value, a first set of programming parameters are used within the programming operation.Type: ApplicationFiled: November 13, 2009Publication date: February 17, 2011Applicant: Nantero, Inc.Inventors: Darlene Hamilton, C. Rinn Cleavelin
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Publication number: 20100103732Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.Type: ApplicationFiled: December 30, 2009Publication date: April 29, 2010Applicant: SPANSION LLCInventors: Sung-Yong Chung, Zhizheng Liu, Yugi Mizuguchi, Xuguang Alan Wang, Yi He, Ming Kwan, Darlene Hamilton, Sung-Chul Lee, Guowei Wang, Nancy Leong
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Patent number: 7692962Abstract: A reduced state memory device and methods of forming and programming multi-level flash memory cell element-pairs of the device, each element configured to store a blank level or two or more program levels are provided. In one embodiment, the reduced state memory device comprises a component configured to store in the memory cell element-pairs one pattern combination of a plurality of program pattern combinations comprising two blank levels, two program levels, and one blank level and one program level, the levels differing by less than a predetermined value. In one embodiment, a method of forming a memory device comprises forming at least one memory device of a multi-level flash memory array, each memory cell comprising two or more memory elements, each memory element configured to store three or more levels, and excluding one or more program pattern combinations that can be stored in the at least one memory cell.Type: GrantFiled: December 18, 2007Date of Patent: April 6, 2010Assignee: Spansion LLCInventors: Darlene Hamilton, Fatima Bathul, Ken Tanpairoj, Ou Li, David Rogers, Roger Tsao
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Patent number: 7679967Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.Type: GrantFiled: December 21, 2007Date of Patent: March 16, 2010Assignee: Spansion LLCInventors: Sung-Yong Chung, Zhizheng Liu, Yugi Mizuguchi, Xuguang Alan Wang, Yi He, Ming Kwan, Darlene Hamilton, Sung-Chul Lee, Guowei Wang, Nancy Leong
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Patent number: 7672803Abstract: A system and method is discussed for providing programmable test conditions for a built-in self test circuit of a flash memory device. The present invention employs a flash memory having BIST circuit for testing the memory and a BIST interface circuit adapted to adjust the test conditions of the memory tests. The BIST interface circuit is operable to receive one or more global variables associated with the test conditions of a plurality of tests used on the flash memory and to output results of the memory tests based on the value of the variables. The global variables are used to adjust the test conditions and to trim one or more references used in various flash memory tests and operations. The system may further include a serial communications medium for communicating the global variables to the BIST interface and test results from the interface.Type: GrantFiled: December 7, 2004Date of Patent: March 2, 2010Assignee: Spansion LLCInventors: Mimi Lee, Darlene Hamilton, Ken Cheong Cheah
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Patent number: 7656705Abstract: Methods of rapidly programming a wordline of multi-level flash memory cells comprising memory cell element-pairs having three or more data levels per bit or element corresponding to three or more threshold voltages are provided. An interactive program algorithm rapidly programs the elements of the wordline of memory cells in a learn phase and a single core programming phase. In one embodiment, each wordline comprises learn element-pairs first programmed to provide learn drain voltages for programming core element-pairs along the wordline having the same program pattern of data levels. A set comprising one or more program patterns is chosen to correspond with each program level used on the wordline. The learn element-pairs are programmed to determine a learned program drain voltage for each program level. This learned program drain voltage essentially provides a wordline and program level specific program characterization of the Vd required for the remaining elements of that wordline.Type: GrantFiled: October 17, 2007Date of Patent: February 2, 2010Assignee: Spansion LLCInventors: Darlene Hamilton, Fatima Bathul, Kulachet Tanpairoj, Ou Li
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Publication number: 20090161462Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.Type: ApplicationFiled: December 21, 2007Publication date: June 25, 2009Applicant: SPANSION LLCInventors: Sung-Yong Chung, Zhizheng Liu, Yugi Mizuguchi, Xuguang Alan Wang, Yi He, Ming Kwan, Darlene Hamilton, Sung-Chul Lee, Guowei Wang, Nancy Leong
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Publication number: 20090154235Abstract: A reduced state memory device and methods of forming and programming multi-level flash memory cell element-pairs of the device, each element configured to store a blank level or two or more program levels are provided. In one embodiment, the reduced state memory device comprises a component configured to store in the memory cell element-pairs one pattern combination of a plurality of program pattern combinations comprising two blank levels, two program levels, and one blank level and one program level, the levels differing by less than a predetermined value. In one embodiment, a method of forming a memory device comprises forming at least one memory device of a multi-level flash memory array, each memory cell comprising two or more memory elements, each memory element configured to store three or more levels, and excluding one or more program pattern combinations that can be stored in the at least one memory cell.Type: ApplicationFiled: December 18, 2007Publication date: June 18, 2009Applicant: SPANSION LLCInventors: Darlene Hamilton, Fatima Bathul, Ken Tanpairoj, Ou Li, David Rogers, Roger Tsao
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Publication number: 20090103357Abstract: Methods of rapidly programming a wordline of multi-level flash memory cells comprising memory cell element-pairs having three or more data levels per bit or element corresponding to three or more threshold voltages are provided. An interactive program algorithm rapidly programs the elements of the wordline of memory cells in a learn phase and a single core programming phase. In one embodiment, each wordline comprises learn element-pairs first programmed to provide learn drain voltages for programming core element-pairs along the wordline having the same program pattern of data levels. A set comprising one or more program patterns is chosen to correspond with each program level used on the wordline. The learn element-pairs are programmed to determine a learned program drain voltage for each program level. This learned program drain voltage essentially provides a wordline and program level specific program characterization of the Vd required for the remaining elements of that wordline.Type: ApplicationFiled: October 17, 2007Publication date: April 23, 2009Inventors: Darlene Hamilton, Fatima Bathul, Kulachet Tanpairoj, Ou Li
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Patent number: 7443732Abstract: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.Type: GrantFiled: September 20, 2005Date of Patent: October 28, 2008Assignee: Spansion LLCInventors: Tiao-Hua Kuo, Nancy Leong, Nian Yang, Guowei Wang, Aaron Lee, Sachit Chandra, Michael A. VanBuskirk, Johnny Chen, Darlene Hamilton, Binh Quang Le