Abstract: A system for communicating high voltages for a semiconductor device is provided. One system includes a controller having an input pad and an output pad, each of the input pad and the output pad being coupled to a respective high voltage switch of the controller. The system also includes a plurality of semiconductor chips, where each of the plurality of semiconductor chips has at least one input pad coupled to a high voltage switch of a respective semiconductor chip. A high voltage that is higher than normal operation voltages of the semiconductor device is coupled from the input pad of the controller to the output pad of the controller via the coupled high voltage switches of the controller. The high voltage is further coupled from the output pad of the controller to the at least one input pad of the respective semiconductor chip via the high voltage switch coupled to the at least one input pad of the respective semiconductor chip.

Abstract: Multi-level encoded data transfer is disclosed. 2n bits may be encoded in a data signal each half clock cycle. For example, four bits may be transferred each clock cycle. Prior to data transfer, each data line may have two bits ready to be encoded. The two bits may be encoded to one of four different data states. The clock may be divided into four intervals for each half clock cycle, with each interval corresponding to one of the four data states. The two bits may be encoded into the data signal based on the interval that corresponds to the data state. As one example, the data signal could transition during the interval that corresponds to the data state for the two bits. This encoding may be repeated for two other bits for the other half of the clock cycle. Thus, QDR or some other data rate may be achieved.

Abstract: A system for communicating high voltages for a semiconductor device is provided. One system includes a controller having an input pad and an output pad, each of the input pad and the output pad being coupled to a respective high voltage switch of the controller. The system also includes a plurality of semiconductor chips, where each of the plurality of semiconductor chips has at least one input pad coupled to a high voltage switch of a respective semiconductor chip. A high voltage that is higher than normal operation voltages of the semiconductor device is coupled from the input pad of the controller to the output pad of the controller via the coupled high voltage switches of the controller. The high voltage is further coupled from the output pad of the controller to the at least one input pad of the respective semiconductor chip via the high voltage switch coupled to the at least one input pad of the respective semiconductor chip.

Abstract: Apparatus and method for coupling high voltages for a semiconductor device via high voltage switches are disclosed. A high voltage switch includes a switch and a level shifter. The switch is defined between a voltage source and a voltage output. An enable line is coupled to a first transistor of the switch. The level shifter includes an input and an output. A characterization line is coupled to the input of the level shifter and the output of the level shifter is coupled to a second transistor of the switch. The level shifter further includes a power rail that is coupled to the switch between the first transistor and the second transistor.

Abstract: Multi-level encoded data transfer is disclosed. 2n bits may be encoded in a data signal each half clock cycle. For example, four bits may be transferred each clock cycle. Prior to data transfer, each data line may have two bits ready to be encoded. The two bits may be encoded to one of four different data states. The clock may be divided into four intervals for each half clock cycle, with each interval corresponding to one of the four data states. The two bits may be encoded into the data signal based on the interval that corresponds to the data state. As one example, the data signal could transition during the interval that corresponds to the data state for the two bits. This encoding may be repeated for two other bits for the other half of the clock cycle. Thus, QDR or some other data rate may be achieved.

Abstract: Apparatus and method for coupling high voltages for a semiconductor device via high voltage switches are disclosed. A high voltage switch includes a switch and a level shifter. The switch is defined between a voltage source and a voltage output. An enable line is coupled to a first transistor of the switch. The level shifter includes an input and an output. A characterization line is coupled to the input of the level shifter and the output of the level shifter is coupled to a second transistor of the switch. The level shifter further includes a power rail that is coupled to the switch between the first transistor and the second transistor.

Abstract: Integrated circuits where the standard isolation cell, at power island boundaries, also includes a protection device, which clamps transient voltages.

Abstract: Timing measurement is performed by a digital oscillator, using a calibration value which is calculated after chip fabrication is completed, and automatically loaded into selection logic at powerup.

Abstract: A digital logic circuit and method for de-glitching an input signal. The circuit removes distortion that occurs during a “de-glitching” time period that follows each transition of the input signal from 0 to 1 or from 1 to 0. The circuit can remove such distortion from the input signal without substantially delaying the input signal. Specifically, the delay interposed can be much less than the duration of the de-glitching time period. One embodiment includes first and second Set-Reset flip-flops each having an input connected to receive the input signal and having an output connected to a majority circuit. A delay circuit also receives the input signal and provides an output to the majority circuit. Other embodiments replace the majority circuit with a circuit including logic gates.

Abstract: Integrated circuits where the standard isolation cell, at power island boundaries, also includes a protection device, which clamps transient voltages.

Abstract: Timing measurement is performed by a digital oscillator, using a calibration value which is calculated after chip fabrication is completed, and automatically loaded into selection logic at powerup.

Abstract: A digital logic circuit and method for de-glitching an input signal. The circuit removes distortion that occurs during a “de-glitching” time period that follows each transition of the input signal from 0 to 1 or from 1 to 0. The circuit can remove such distortion from the input signal without substantially delaying the input signal. Specifically, the delay interposed can be much less than the duration of the de-glitching time period. One embodiment includes first and second Set-Reset flip-flops each having an input connected to receive the input signal and having an output connected to a majority circuit. A delay circuit also receives the input signal and provides an output to the majority circuit. Other embodiments replace the majority circuit with a circuit including logic gates.