Abstract: A system and method are provided for moving information between cache coherent memory systems of a partitioned multiprocessor computer system while containing faults to a single partition. The multiprocessor computer system includes a plurality of processors, memory subsystems and input/output (I/O) subsystems that can be divided into a plurality of partitions. Each I/O subsystem includes at least one I/O bridge for interfacing between one or more I/O devices and the multiprocessor system. The I/O bridge has a data mover configured to retrieve information from a “source” partition and to store that information within its own “destination” partition. When activated, the data mover issues a request to the source partition for a non-coherent copy of the information. The home memory subsystem in the source partition preferably responds to the request by sending the data mover “valid”, but non-coherent copy of the information, e.g.

Abstract: A system and method are provided for moving information between cache coherent memory systems of a partitioned multiprocessor computer system while containing faults to a single partition. The multiprocessor computer system includes a plurality of processors, memory subsystems and input/output (I/O) subsystems that can be divided into a plurality of partitions. Each I/O subsystem includes at least one I/O bridge for interfacing between one or more I/O devices and the multiprocessor system. The I/O bridge has a data mover configured to retrieve information from a “source” partition and to store that information within its own “destination” partition. When activated, the data mover issues a request to the source partition for a non-coherent copy of the information. The home memory subsystem in the source partition preferably responds to the request by sending the data mover an “valid”, but non-coherent copy of the information, e.g.

Abstract: An open drain driver, differential receiver circuit for transmitting logic signals generated by metal oxide semiconductor (MOS) logic circuits over a data bus that uses distributed termination impedances. The distributed termination impedance values are chosen to minimize the data bus settling time both when a driver in a given module drives a signal consisting of alternating logic levels, as well as when two different drivers drive a given logic level in succession. Each open drain driver includes a multiplexor, a flip flop, an inverter stage, and a driver transistor. The multiplexor selects either a data signal to be transmitted or a deasserted data value to be passed to the input of the flip flop. The flip flop also accepts a test input, which sets the flip flop to a known state. As a result, no additional delay is inserted in the critical path between the rising edge of a flip flop clock input signal and the driver output.

Abstract: A cache coherency protocol for a multi-processor system which provides for read/write, read-only and transitional data states and for an indication of these states to be stored in a memory directory in main memory. The transitional data state occurs when a processor requests from main memory a data block in another processor's cache and the request is pending completion. All subsequent read requests for the data block during the pendency of the first request are inhibited until completion of the first request. Also provided in the memory directory for each data block is a field for identifying the processor which owns the data block in question. Data block ownership information is used to determine where requested owned data is located.

Abstract: A power supply interlock technique for an electronic system which uses metal oxide semiconductor (MOS) logic circuits require two or more different supply voltages, and where each circuit board module contains its own power supplies. An open-collector enable signal is both controlled and sensed by each of the modules. The enable signal is set true when all of the supplies in the system are operating properly. However, the enable signal is set false by any one of the modules if one of the higher voltage supplies on that module is malfunctioning. The enable line also controls the lower voltage power supplies in each module. None of the lower voltage power supplies is thus permitted to operate until the enable line is set true, which occurs only when all of the modules indicate they have an operating high voltage supply available. As a result, latch-up of parasitic transistors in the circuits which drive logic signals on a system bus is avoided.

Abstract: A node includes logic circitry for transmitting and receiving data on a backplane bus. The driver in the transmitting logic in the node acts with the current source provided by the bus to decrease the transition time of the data transmitted onto the bus. A coupling resistor is included in the node for individually coupling the driver in the node to the bus for limiting voltage excursions on the bus and providing impedance matching between the node and bus and permitting driver overlap at the bus so that higher speed and lower power dissipation occurs. In the preferred embodiment, CMOS logic circuitry is utilized.

Abstract: A node for obtaining access to a bus. In this arbitration method, the node receives a conditional grant. The node determines whether access to the bus will actually transfer to it. The node contains distributed logic that examines an extend bus cycle signal to determine whether it can become a transmitter to transfer messages on the bus. When the node becomes a transmitter, it generates an extend bus cycle signal to maintain access to the bus when executing a multi-cycle transfer, even though other nodes, perhaps with higher priorites, require access to the bus.

Abstract: A node for obtaining access to a bus. In this arbitration method, the node receives a conditional grant. The node determines whether access to the bus will actually transfer to it. The node contains distributed logic that examines an extend bus cycle signal to determine whether it can become a transmitter to transfer messages on the bus. When the node becomes a transmitter, it generates an extend bus cycle signal to maintain access to the bus when executing a multi-cycle transfer, even though other nodes, perhaps with higher priorities, require access to the bus.

Abstract: A node for communicating with a plurality of other nodes in a computer, the node including logic circuitry for transmitting and receiving data at first and second logic levels. A default generator is connected to an arbiter and responds to a lack of request activity and the absence of a multi-cycle data transfer being performed on the bus and causes the bus to be driven to one of the first and second logic levels.

Abstract: A system and method for nodes to obtain access to a bus. In this arbitration method, a central arbiter selects a particular node and issues a conditional grant. The conditional grant is transmitted before it is determined whether access to the bus will actually transfer to another node. Each node contains distributed logic that examines an extend bus cycle signal to determine whether it can become a transmitter to transfer messages on the bus. When a node becomes a transmitter, it generates an extend bus cycle signal to maintain access to the bus when executing a multi-cycle transfer, even though other nodes, perhaps with higher priorities, require access to the bus.

Abstract: A node for obtaining access to a bus. In this arbitration method, the node receives a conditional grant. The node determines whether access to the bus will actually transfer to it. The node contains distributed logic that examines an extend bus cycle signal to determine whether it can become a transmitter to transfer messages on the bus. When the node becomes a transmitter, it generates an extend bus cycle signal to maintain access to the bus when executing a multi-cycle transfer, even though other nodes, perhaps with higher priorities, require access to the bus.

Abstract: A system for communicating between a plurality of nodes in a computer, each node including logic circuitry for transmitting and receiving data. The subject system includes (1) a backplane bus for carrying the data between the nodes, (2) a driver in each node and a current source circuit coupled to the bus which drive the bus in parallel to decrease the transition time of the data transmitted onto the bus, and (3) coupling resistors individually coupling the bus to the driver in each node and providing impedance matching between the bus and nodes and permitting driver overlap at the bus so that the higher speed and lower power dissipation occurs. In the preferred embodiment, CMOS logic circuitry is utilized and resistors are used to terminate the ends of the bus to the supply voltages.

Abstract: A system for communicating between a plurality of nodes in a computer, each node including logic circuitry or transmitting and receiving data at first and second logic levels. The system includes an arbiter coupled to the nodes for detecting a lack of request activity from the nodes. A default generator is connected to the arbiter and responds to a lack of request activity and the absence of a multi-cycle data transfer being performed on the bus and causes the bus to be driven to one of the first and second logic levels.

Abstract: An interface system between a high speed user bus and a system bus is provided to present to the user bus a picture of the data transferred on the system bus every clock cycle of that system bus. The interface system also allows the user bus to transfer data back to the system bus during selected bus cycles. By using a single pin connection to the system bus, the user bus can send communications back to itself by way of the system bus.

Abstract: Bus interface apparatus is provided to drive a high speed bus with two nonoverlapping clock signals. The apparatus takes advantage of the inherent bus capacitance which will temporarily hold data signals placed on the bus by using bus interface circuitry having high input and output impedances. That circuitry can thus be activated by coincident signals.

Abstract: An electronic circuit configured to pass relatively high voltage signals therethrough when enabled, and block both positive and negative signals when appropriately disabled. The features of the circuit are particularly suited for coupling write and erase voltages to a nonvolatile memory array while integrated on a common chip with the array. In one form, the circuit includes a two-phase pump, which upon being enabled draws a transient current from the high voltage input line and raises the voltage level on an internal capacitive node in closed loop fashion by effecting unidirectional transfers of charge between successive capacitive nodes. The elevated internal voltage provides a driving signal to a driving circuit which passes the high voltage on the input line to an output line without incurring threshold voltage losses.

Abstract: A volatile/non-volatile RAM cell employing a bistable multivibrator with non-volatile, alterable-threshold capacitors coupled to the output terminals thereof to provide backup data storage in a power-down situation. In one embodiment, the non-volatile capacitors each have a non-alterable section and an alterable section, the non-alterable section having either a depletion or an enhancement threshold. The V/NV RAM cell employs a pair of field effect transistors of depletion or enhancement type to couple the non-volatile capacitors to the output terminals. These coupling transistors form with the non-volatile capacitors a pair of nodes. The coupling transistors are biased such that a write voltage signal applied to the gates of the non-volatile capacitors produces a bootstrapped voltage on one of the pair of nodes which is effectively isolated from the output terminals of the cell.