Abstract: Embodiments related to re-dispatching an instruction selected for re-execution from a buffer upon a microprocessor re-entering a particular execution location after runahead are provided. In one example, a microprocessor is provided. The example microprocessor includes fetch logic, one or more execution mechanisms for executing a retrieved instruction provided by the fetch logic, and scheduler logic for scheduling the retrieved instruction for execution. The example scheduler logic includes a buffer for storing the retrieved instruction and one or more additional instructions, the scheduler logic being configured, upon the microprocessor re-entering at a particular execution location after runahead, to re-dispatch, from the buffer, an instruction that has been previously dispatched to one of the execution mechanisms.

Abstract: Embodiments related to re-dispatching an instruction selected for re-execution from a buffer upon a microprocessor re-entering a particular execution location after runahead are provided. In one example, a microprocessor is provided. The example microprocessor includes fetch logic, one or more execution mechanisms for executing a retrieved instruction provided by the fetch logic, and scheduler logic for scheduling the retrieved instruction for execution. The example scheduler logic includes a buffer for storing the retrieved instruction and one or more additional instructions, the scheduler logic being configured, upon the microprocessor re-entering at a particular execution location after runahead, to re-dispatch, from the buffer, an instruction that has been previously dispatched to one of the execution mechanisms.

Abstract: A method and apparatus are provided for entering and exiting multiple threads within a multithreaded processor. A state machine is maintained to indicate a respective status of an associated thread of multiple threads being executed within a multithreaded processor. A change of status for a first thread within the multithreaded processor is detected and, responsive to the change of status for the first thread within the multithreaded processor, a partitioning scheme for the functional unit is altered to service a second thread, but not the first thread, within the multithreaded processor when the change of the status of the first thread comprises a transition from an active state to an inactive state.

Abstract: A system includes a multithreaded processor, a memory to store the plurality of threads, and a bus to deliver the plurality of threads to the multithreaded processor. The multithreaded processor includes an event detector to detect a first event indication for a first thread. The event detector, responsive to the detection of the first event indication for the first thread, monitors a second thread being processed within the multithreaded processor to detect a clearing point for the second thread and, responsive to the detection of the clearing point for the second thread clears a functional unit within the multithreaded processor for at least the first thread.

Abstract: A digital signal processor having a generalized bit field extraction instruction which can be used to perform a bit field selection operation, a rotate left operation, a rotate right operation, a shift left operation, a logical shift right operation, an arithmetic shift right operation, and so forth.

Abstract: A digital signal processor which uses a RISC/CISC style front end and a VLIW style back end. Sequential ISA instructions are decoded into ?ops having a programmatic ordering. The ?ops are packed into a VLIW-like instruction packet according to a set of rules enforcing machine policy on e.g. data dependency, VLIW slot availability, maximum VLIW width, and so forth. Within the instruction packet, original program order is identified in case it is necessary to perform precise exception handling. The ISA code is executed as though it were on a RISC/CISC machine, but with VLIW style ILP efficiencies.

Abstract: Method, apparatus, and system for a programmable event driven yield mechanism that may activate other threads. The yield mechanism may allow triggering of a service thread that may execute currently with a main thread upon occurrence of an architecturally-defined condition. The service thread may be activated, in response to the condition, with limited intervention of an operating system. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect an architecturally-defined condition. The apparatus may include an event handler to handle a yield event generated when the architecturally-defined condition has been detected. An architectural mechanism, including processor instructions and channel registers, may be utilized to allow user-level code to enable the yield event mechanism. Other embodiments are also described and claimed.

Abstract: A processor having an architecture including an instruction with a source operand from which the processor derives at least one of an operand value and a control value. The source operand may directly specify the operand value or the control value, with the other being implicitly specified. Or, both may be implicitly specified and derived from the source operand value. At least one of the operand value and the control value is implicit, not specified. An ADDSRN instruction which performs addition and right shifting and rounding, in which one of the source operands is an encoded immediate which specifies the shift count N. The processor corrects after the addition and shifting for an absent rounding bias added 2N-1. The ADDSRN instruction is used in accelerating digital signal processing code sequences of the form dest:=(A+B+C+D . . .

Abstract: A processor having an architecture including an instruction with a source operand from which the processor derives at least one of an operand value and a control value. The source operand may directly specify the operand value or the control value, with the other being implicitly specified. Or, both may be implicitly specified and derived from the source operand value. At least one of the operand value and the control value is implicit, not specified. An ADDSRN instruction which performs addition and right shifting and rounding, in which one of the source operands is an immediate which specifies the shift count N and the processor derives a third added 2N?1, and the ADDSRN instruction is used in accelerating digital signal processing code sequences of the form dest:=(A+B+C+D . . .

Abstract: A processor having an architecture including an instruction with a source operand from which the processor derives at least one of an operand value and a control value. The source operand may directly specify the operand value or the control value, with the other being implicitly specified. Or, both may be implicitly specified and derived from the source operand value. At least one of the operand value and the control value is implicit, not specified.

Abstract: A processor ISA instruction which performs a clipping operation forcing a data element to be within a specified range. A SIMD processor ISA instruction which performs a clipping operation upon each data element in a source operand vector. A SIMD processor ISA instruction which performs clipping upon each data elements in each of a plurality of source operand vectors, and performs picking, rounding, and packing upon the clipped operand vectors to generate a single result vector.

Abstract: A processor ISA instruction which performs a clipping operation forcing a data element to be within a specified range. A SIMD processor ISA instruction which performs a clipping operation upon each data element in a source operand vector.

Abstract: A method includes detecting a first pending event related a first thread being processed within a multithreaded processor. Responsive to the detection of the first pending event, a second thread being processed within the multithreaded processor is monitored to detect an event handling point for the second thread. Responsive to the detection of the event handling point for the second thread, at least a first event handler is invoked to handle at least the first pending event.

Abstract: A register file in which the physical row/column mapping is decoupled from the logical row/column mapping. The physical register file includes R*C N-bit storage elements arranged in R rows and C columns. Each physical row includes an N-bit bus, a log2(C)-bit storage element selection line, and a log2(C)-bit output column selection line. In either a logical row or logical column access, no more than one storage element is selected per physical row and coupled to that row's bus, and each column's vertical bit line is uniquely coupled to one row's bus. The values on the storage element selection lines and on the output column selection lines determines which storage elements are coupled to which vertical bit lines. The width C of the register file, the number of rows R of the register file, and the size N of the fundamental data storage element can be independently changed without affecting the others.

Abstract: In a microprocessor, customer code routines are decoded from ISA instructions into microinstructions and stored in a customer code store (CCS) for later, repeated execution. Branch target addresses in the ISA code, which use an ISA memory addressing format, are replaced with CCS branch target addresses in the decoded, stored customer code routine. The customer code routine thus behaves as a microcoded library routine.

Abstract: A microprocessor including memory storage into which ISA customer code routines can be stored after having been decoded into their machine-native microinstructions. The customer code store is not subject to eviction and the like, as a cache memory would be. ISA level code can specify a routine for storage into the customer code store, at a time prior to its execution. The customer code store thus serves as a write-once execute-many library of pre-decoded routines which ISA level applications can subsequently use, permitting a system manufacturer to create a highly customized and optimized system.

Abstract: A system includes a multithreaded processor, a memory to store the plurality of threads, and a bus to deliver the plurality of threads to the multithreaded processor. The multithreaded processor includes an event detector to detect a first event indication for a first thread. The event detector, responsive to the detection of the first event indication for the first thread, monitors a second thread being processed within the multithreaded processor to detect a clearing point for the second thread and, responsive to the detection of the clearing point for the second thread clears a functional unit within the multithreaded processor for at least the first thread.

Abstract: A method includes maintaining a state machine to provide a multi-bit output, each bit of the multi-bit output indicating a respective status for an associated thread of multiple threads being executed within a multithreaded processor. Status for a first thread is detected, responsive to which a functional unit within the multithreaded processor is configured in accordance with the multi-bit output of the state machine.

Abstract: A method and apparatus are provided for entering and exiting multiple threads within a multithreaded processor. A state machine is maintained to indicate a respective status of an associated thread of multiple threads being executed within a multithreaded processor. A change of status for a first thread within the multithreaded processor is detected and, responsive to the change of status for the first thread within the multithreaded processor, a partitioning scheme for the functional unit is altered to service a second thread, but not the first thread, within the multithreaded processor when the change of the status of the first thread comprises a transition from an active state to an inactive state.

Abstract: According to one aspect of the invention, a microprocessor is provided that includes an execution core, a first replay mechanism and a second replay mechanism. The execution core performs data speculation in executing a first instruction. The first replay mechanism is used to replay the first instruction via a first replay path if an error of a first type is detected which indicates that the data speculation is erroneous. The second replay mechanism is used to replay the first instruction via a second replay path if an error of a second type is detected which indicates that the data speculation is erroneous.